JPS609152A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS609152A
JPS609152A JP58115878A JP11587883A JPS609152A JP S609152 A JPS609152 A JP S609152A JP 58115878 A JP58115878 A JP 58115878A JP 11587883 A JP11587883 A JP 11587883A JP S609152 A JPS609152 A JP S609152A
Authority
JP
Japan
Prior art keywords
cell array
peripheral circuit
semiconductor device
regions
circuit region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58115878A
Other languages
English (en)
Other versions
JPS64822B2 (ja
Inventor
Yoshihiro Takemae
義博 竹前
Tomio Nakano
中野　富男
Kimiaki Sato
公昭 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58115878A priority Critical patent/JPS609152A/ja
Priority to US06/625,682 priority patent/US4660174A/en
Priority to EP84304391A priority patent/EP0130798B1/en
Priority to DE8484304391T priority patent/DE3485625D1/de
Priority to KR1019840003724A priority patent/KR910005597B1/ko
Publication of JPS609152A publication Critical patent/JPS609152A/ja
Publication of JPS64822B2 publication Critical patent/JPS64822B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B17/00—Layered products essentially comprising sheet glass, or glass, slag, or like fibres
    • B32B17/06—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material
    • B32B17/10—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material of synthetic resin
    • B32B17/10005—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material of synthetic resin laminated safety glass or glazing
    • B32B17/10807—Making laminated safety glass or glazing; Apparatus therefor
    • B32B17/10816—Making laminated safety glass or glazing; Apparatus therefor by pressing
    • B32B17/10825—Isostatic pressing, i.e. using non rigid pressure-exerting members against rigid parts
    • B32B17/10834—Isostatic pressing, i.e. using non rigid pressure-exerting members against rigid parts using a fluid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
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    • B32B17/00—Layered products essentially comprising sheet glass, or glass, slag, or like fibres
    • B32B17/06—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material
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    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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  • Semiconductor Integrated Circuits (AREA)
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  • Semiconductor Memories (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 発明の技術分野 本発明は半導体装置、特に、そのレイアウトに関する。
技術の背景 半導体装置として、たとえばダイナミックＲＡＭ、スタ
ティックＲＡＭのレイアウトとしては、主に、セルアレ
イ領域、周辺回路領域、およびゾンデイングツ臂ツド領
域に分けられる。この場合、セルアレイ領域には、ワー
ド線もしくはビット線毎に規則的な繰返しノやターンと
して設けられた回路たとえばセルアレイ、デコーダ、セ
ンスアンプ等力配置される。他方、周辺回路領域には、
ワード線もしくはビット線毎に設けられず、言い換える
と、不規則的ノやターンの回路が配置される。このよう
なセルアレイ領域、周辺回路領域、ポンプイングツ９ツ
ド領域等のレイアウトは半導体装置の欠容量化の点で重
要なことである。
従来技術と問題点 従来の半導体装置を第１図に示す。第１図にはたとえば
工６ピンダイナミ、りＲＡＭを示しである。
第１図において、デコーダ、センスアンプ等ｔ−モ含む
セルアレイ領域１の両側に周辺回路領域２−１゜２−２
を設けてあり、さらにその外側にがンデバンダノ臂ツド
Ｐｌ”Ｐｉｅが設けられている。ここで、パッドＰ１６
がｖｌ１８電源用であシ、パッドＰ８がｖｃ０電源用で
ある。なお、Ｍ１図の装置はＤＩＰ（プーアルイン２イ
ンノ？ツケージ）に実装する場合を想定してｈる。
第１図においては、各周辺回路領域２−１．２−２共も
パッドＰ１〜Ｐ１６から信号を受けなければならない。
従って、周辺回路領域２−１に対しては領域Ｘ、Ｙを介
してパッドＰ５〜Ｐｉ１１が接続され、他方、周辺回路
領域２−２に対しても領域Ｘ、Ｙを介してパッドＰ１　
”’＝Ｐ　４　ｒ　Ｐ　１３〜ｐｔｏが接続されること
になる。たとえば、領域Ｘ、Ｙにおける信号線として、
ノクッドＰ８およびｐｔａの各屯源線幅は、抵抗を十分
低くするために、１００μｍ程度必要とする。また、そ
の他の信号線幅も６μｍ程度必要とし、その数はこの場
合、２０〜３０である。従って、領域Ｘ、Ｙにおける総
信号線幅は、 １００Ｘ２＋６Ｘ（２０〜３０） ＝３００〜４００珈 となシ、これはセルアレイ領域１の面積を制限する要因
となり、大容量化の点で不利である。しかも、第１図の
装置全す−ディープ又はグラスチック型・ぐツケーノに
実装すれば、第２図に示すように、・フッドとリードと
の間を接続するワイヤＷを短かくしてその容量を少さく
すると、たとえば、−３番ビンのリード４−３と４番ピ
ンのリード４−４とが重なる部分２が生じ、これも第１
図の装置の面積を制限するものであｐ１従って、やはシ
、大容量化の点で不利となる。
発明の目的 本発明の目的は、上述の従来形における問題点に鑑み、
セルアレイ領域を２分割し、その間に周辺回路領域を設
けることによシ、周辺回路領域と・フッドとの間におけ
る信号線のトータル幅を減少させ、つまシ、第１図の領
域Ｘ、Ｙの幅を低減して大容量イヒを達成することにあ
る。
発明の構成 上述の目的を達成するために本発明によれば、規則性的
繰返し・ぐターンからなる回路ブロックを２分割し、該
２分割された回路ブロックの間に不規則的パターンを有
する周辺回路全配置し、前記２分割された回路ブロック
の外側に？ンディングノ卆ツド領域を設けた半導体装置
が提供される。
発明の実施例 以下、図面によｐ本発明の詳細な説明する。
第３図は本発明に係る半導体装置の一実施例を示すレイ
アウト図である。第３図においては、左右に、セルアレ
イ領域１−１．１−２を設け、その間に周辺回路領域２
が設けられている。さらに、各セルアレイ領域１−１．
１−２の外側に？ンディングＡ　ラドを設けである。な
お、ノ４．ドＰ４＋ｐ５　、ｐｍ□、ＰＩ３のみが中央
部に設けられているのはサーブ渇スチツク・々ツケーゾ
に実装する場合を想定しているからであり、Ｄ工Ｐに実
装する場合にはこれらのノ臂ツドもセルアレイ領域１−
１．１−２の外側に設けられる。
第３図においては、周辺回路領域２と電源用ノ４１ッド
Ｐｇ＋Ｐｔａとの距離は第１図の場合に比べてほぼ１／
２となり、従って、抵抗値を考慮すれば、周辺回路２と
電源用・々ツドＰｓ＋Ｐｘｓとを接続する電源線の幅は
１７２でよく、シかも、領域Ｘ’ｌＹ’を通過する電源
線の本数も１／２となる。従って、領域ｘ　／　、ｙ　
／における総信号線幅は、他の信号線を考慮しても、第
１図の場合に比べてほぼ１／４にナル。なお、セルアレ
イ領域１−１とｘ−２（７）両側の領域Ｘ／　Ｙ　／は
それぞれ異なる本数の信号線が配線されるため、セルア
レイ領域のＹ軸方向の位置は異なることがある。
第３図の装置をサーブイブ又はゲラステック型・やツケ
ージに実装すれば、第４図に示すように、３番ピンのり
−ド４−３と４番ピンのリード４−４とが重複せず、従
って、ノや、ケージに余裕が生じ、延いては、第３図の
装置の大容量化に役立つものである。
発明の詳細 な説明したように本発明によれば、セルアレイ領域外の
総信号線幅を減少させることができ、従って、装置の大
容量化を達成できる。
【図面の簡単な説明】
第１図は従来の半導体装置のレイアウト図、第２図は第
１図の装置をサーディググラスチックノ母ッケージに実
装した場合の部分レイアウト図、第３図は本発明に係る
半導体装置の一実施例を示すレイアウト図、第４図は第
３図の装置をサーｒイププラスチックノやツケーゾに実
装した場合の部分レイアウト図である。 １−１．１−２：セルアレイ領域（規則性回路λ２二周
辺回路（不規則〕ぐターン回路）、ＰＩ　ＩＰ１６］ポ
ンディングパッド。 特許出願人 富士通株式会社 特許出願代理人 弁理士　青　木　朗 弁理士　西　舘　和　之 弁理士　内　１）幸　男 弁理士　山　口　昭　之 第１図 第２図 第３図 第４日 手続補正書（自発） 昭和５９年５月−）３日 特許庁長官　若　杉　和　夫　殿 １、事件の表示 昭和５８年特許願第１１５８７８号 ２、発明の名称 半導体装面 ３　補正をする者 事件との関係　特許出願人 名称（５２２）富士通株式会社 ４、代理人 住所　〒１０５東京都港区虎ノ門−丁目８番１０号１、
）明細書の「発明の詳細な説明」の欄２）明細書の「図
面の簡単な説明」の欄６、補正の内容 １）Ａ）明細書第２頁第２行目 「ワード線」の前に「回路は」を挿入する。 Ｂ）明細書第５頁第２０行目 「Ｘ’Ｙ’Ｊ　？　ｒ　ｘ’、　ｙ’、３　色補正−１
−ル。 ２）Ａ）明細書第６頁第１５行目、および第１８行から
第１９行目 「サーディプ」の後に「またはＪを挿入する。 Ｂ）明細書第７頁第１行目 「（規則性回路）」を削除する。 Ｃ）明細書第７頁第２行目 「（不規則・９タ一ン回路）」をｒ領域」と補正する。 Ｄ）明細書第７頁第２行目 「Ｐｌ、Ｐ、６」をｒｐ、〜Ｐ、６」と補正する。

Claims (1)

    【特許請求の範囲】
  1. １、規則的繰返しＡターンからなる回路ブロックを２分
    割し、該２分割された回路ブロックの間に不規則的パタ
    ーン金有する周辺回路を配置し、前記２分割された回路
    ブロックの外側にがンディングパッド領域を設けた半導
    体装置。
JP58115878A 1983-06-29 1983-06-29 半導体装置 Granted JPS609152A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP58115878A JPS609152A (ja) 1983-06-29 1983-06-29 半導体装置
US06/625,682 US4660174A (en) 1983-06-29 1984-06-28 Semiconductor memory device having divided regular circuits
EP84304391A EP0130798B1 (en) 1983-06-29 1984-06-28 Semiconductor memory device
DE8484304391T DE3485625D1 (de) 1983-06-29 1984-06-28 Halbleiterspeicheranordnung.
KR1019840003724A KR910005597B1 (ko) 1983-06-29 1984-06-29 분할된 정류회로를 가진 반도체 기억장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58115878A JPS609152A (ja) 1983-06-29 1983-06-29 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP1324891A Division JPH077819B2 (ja) 1989-12-16 1989-12-16 半導体記憶装置

Publications (2)

Publication Number Publication Date
JPS609152A true JPS609152A (ja) 1985-01-18
JPS64822B2 JPS64822B2 (ja) 1989-01-09

Family

ID=14673401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58115878A Granted JPS609152A (ja) 1983-06-29 1983-06-29 半導体装置

Country Status (5)

Country Link
US (1) US4660174A (ja)
EP (1) EP0130798B1 (ja)
JP (1) JPS609152A (ja)
KR (1) KR910005597B1 (ja)
DE (1) DE3485625D1 (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61278160A (ja) * 1985-05-31 1986-12-09 シ−メンス、アクチエンゲゼルシヤフト 半導体集積回路用接続装置
JPS62122139A (ja) * 1985-11-21 1987-06-03 Nec Corp 半導体記憶装置
JPS62147763A (ja) * 1985-12-20 1987-07-01 Nec Corp 半導体記憶装置
JPS62180594A (ja) * 1986-02-04 1987-08-07 Fujitsu Ltd 半導体記憶装置
JPS6379871U (ja) * 1986-11-14 1988-05-26
JPH0250438A (ja) * 1988-08-12 1990-02-20 Hitachi Ltd 半導体記憶装置
JPH02114562A (ja) * 1988-10-24 1990-04-26 Nec Corp 半導体記憶装置
USRE36236E (en) * 1989-10-05 1999-06-29 Kabushiki Kaisha Toshiba Semiconductor memory device
KR100380409B1 (ko) * 2001-01-18 2003-04-11 삼성전자주식회사 반도체 메모리 소자의 패드배열구조 및 그의 구동방법

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3585756D1 (de) * 1984-07-02 1992-05-07 Fujitsu Ltd Halbleiterschaltungsanordnung in hauptscheibentechnik.
JPH0652784B2 (ja) * 1984-12-07 1994-07-06 富士通株式会社 ゲートアレイ集積回路装置及びその製造方法
JPS61227289A (ja) * 1985-03-30 1986-10-09 Fujitsu Ltd 半導体記憶装置
JPS62192086A (ja) * 1986-02-18 1987-08-22 Matsushita Electronics Corp 半導体記憶装置
US5265045A (en) * 1986-10-31 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit device with built-in memory circuit group
US5243208A (en) * 1987-05-27 1993-09-07 Hitachi, Ltd. Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
US5287000A (en) * 1987-10-20 1994-02-15 Hitachi, Ltd. Resin-encapsulated semiconductor memory device useful for single in-line packages
DE3776798D1 (de) * 1987-11-23 1992-03-26 Philips Nv Schnell arbeitender statischer ram-speicher mit grosser kapazitaet.
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
US5278802A (en) * 1988-10-28 1994-01-11 Texas Instruments Incorporated Decoding global drive/boot signals using local predecoders
JPH0772991B2 (ja) * 1988-12-06 1995-08-02 三菱電機株式会社 半導体記憶装置
US6069814A (en) * 1989-05-26 2000-05-30 Texas Instruments Incorporated Multiple input buffers for address bits
EP0428785B1 (de) * 1989-11-24 1994-02-16 Siemens Aktiengesellschaft Halbleiterspeicher
JP3242101B2 (ja) * 1990-10-05 2001-12-25 三菱電機株式会社 半導体集積回路
JPH05308136A (ja) * 1992-04-01 1993-11-19 Nec Corp マスタスライス集積回路
JP3073610B2 (ja) * 1992-09-22 2000-08-07 株式会社東芝 半導体記憶装置
US5517442A (en) * 1995-03-13 1996-05-14 International Business Machines Corporation Random access memory and an improved bus arrangement therefor
US5936877A (en) 1998-02-13 1999-08-10 Micron Technology, Inc. Die architecture accommodating high-speed semiconductor devices
DE19907922C1 (de) 1999-02-24 2000-09-28 Siemens Ag Leseverstärkeranordnung mit gemeinsamen durchgehendem Diffusionsgebiet der Leseverstärker-Transistoren

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals
JPS5258327A (en) * 1975-11-08 1977-05-13 Hitachi Ltd Semiconductor memory unit
US4527254A (en) * 1982-11-15 1985-07-02 International Business Machines Corporation Dynamic random access memory having separated VDD pads for improved burn-in

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61278160A (ja) * 1985-05-31 1986-12-09 シ−メンス、アクチエンゲゼルシヤフト 半導体集積回路用接続装置
JPS62122139A (ja) * 1985-11-21 1987-06-03 Nec Corp 半導体記憶装置
JPH0564852B2 (ja) * 1985-11-21 1993-09-16 Nippon Electric Co
JPS62147763A (ja) * 1985-12-20 1987-07-01 Nec Corp 半導体記憶装置
JPS62180594A (ja) * 1986-02-04 1987-08-07 Fujitsu Ltd 半導体記憶装置
JPS6379871U (ja) * 1986-11-14 1988-05-26
JPH0250438A (ja) * 1988-08-12 1990-02-20 Hitachi Ltd 半導体記憶装置
JPH02114562A (ja) * 1988-10-24 1990-04-26 Nec Corp 半導体記憶装置
USRE36236E (en) * 1989-10-05 1999-06-29 Kabushiki Kaisha Toshiba Semiconductor memory device
KR100380409B1 (ko) * 2001-01-18 2003-04-11 삼성전자주식회사 반도체 메모리 소자의 패드배열구조 및 그의 구동방법

Also Published As

Publication number Publication date
JPS64822B2 (ja) 1989-01-09
US4660174A (en) 1987-04-21
DE3485625D1 (de) 1992-05-07
EP0130798A3 (en) 1988-08-31
KR910005597B1 (ko) 1991-07-31
EP0130798B1 (en) 1992-04-01
EP0130798A2 (en) 1985-01-09
KR850000124A (ko) 1985-02-25

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