JPS607758A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS607758A
JPS607758A JP58115533A JP11553383A JPS607758A JP S607758 A JPS607758 A JP S607758A JP 58115533 A JP58115533 A JP 58115533A JP 11553383 A JP11553383 A JP 11553383A JP S607758 A JPS607758 A JP S607758A
Authority
JP
Japan
Prior art keywords
film
bump
electrode
slit
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58115533A
Other languages
English (en)
Inventor
Shigeru Ozora
大空　茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58115533A priority Critical patent/JPS607758A/ja
Publication of JPS607758A publication Critical patent/JPS607758A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 不発明は、半導体基板のバンプ電極に熱圧着でリードフ
レームを直接接着組立てる半導体装置に関する・ このような半導体装置の場合、その組立工程では、半導
体基板外部引き出し電極として、金属ノくンプ上面へ、
テープキャリアのフィンガーリード、または、リードフ
レームを熱圧着して組立てられる。この時の熱と１強大
な印加圧力のために生ずる応力の大部分を、バンプ部で
吸収しなければならず、バンプ部下方に位置する絶縁膜
に対するストレスも相当なもので、バンプ下方の構造を
含めた金属バンプは、これに剛える構造が必要とされる
。しかしながら、従来のバンプ部は必ずしも充分な耐力
を有するものとはいえない。
すなわち、第１図は従来の半導体装置のバング電極部の
断面図である。第１図において、１は通常の熱拡散層を
含むシリコン基板、２は熱収化膜。
輩化膜等よシ成る絶縁膜、３ａ、３ｂ、３’ｃはそれぞ
れチタン膜、白金膜、金膜で、この３層膜はその一部バ
ンプ領域全内包する内部配線で、１４が、例えば金等か
ら成る金属バンプ電極である。
この従来のバンプ部構造から生ずる欠点としては、その
組立工程で、半導体基板引き出し電極としてのバンプ部
上面に、外部電極でめるテープキャリアのフィンガーリ
ード、またはリードフレームを熱圧着するが、この時に
印加される熱と圧力に対し、バンプ部下方で応力集中を
起こし％騒人なストレスとなって下方の絶縁膜を破壊（
いわゆるクラック）する。さらには、下方の基板シリコ
ンにまで達するクラック金主じて、従来型半導体装置の
信頼度を著しく低下させていた。
不発明の目的は、リードフレームなどの熱圧着に際し、
何らの損傷もバンプ部に生じないようにされた半導体装
置を１是供することにある。
本発明の半導体装置は、テープキャリアのフィンガーリ
ードまたはリードフレームなどを熱圧着で接続するバン
プ部は、下層部では複数個の小バンプ部に分かれており
、上層部では一体化されて一つのバンプに構成され、上
記熱圧着の際の応力はバンプ内で分散させることによシ
緩和し、バンプ部の絶縁膜および基板の損傷が防止され
ている。
つぎに本発明を実施例により説明する。
第２図（ａ）〜（Ｃ）は不発明全製造工程によって説明
するための工程途中の半導体基板バンプ部の断面図で、
同図（ｄ）、　（ｅ）は最終工程後の前記基板バンプ部
の平面図とそのＡ−Ａ断面図である。まず、第２図（ａ
）のように、熱拡散層などを含むシリコン基板１の上の
絶縁膜２に接続窓５をあけだ後で、配線パターン形成の
だめの７オトレジスト膜６を形成し、それから、チタン
膜３ａ、白金膜３ｂを重ねて＃Ｎする。この場合、内部
配線のバンプ部には、小バンプに分割するためのスリッ
トヲ作るレジスト膜７を残している。つきに、第２図（
ｂ）のように、リニノトオフでレジスト膜６の上のチタ
ン、白金が除去され、バンプ部領域に、バンプをη数の
小バンプに分割するスリッ）７ａが設けられる。
さらに、公知のメッキ技術で、ホトレジスト９をマスク
にアルミニウム８ｆｔ、、メッキ導電ｊ良として、チタ
ン・白金上方にのみ内部配縁としての金膜３ｃが２〜３
μｎ１メツキ形成される。金はチタン、白金上方にのみ
析出する。つぎに第２図（Ｃ）のように、ホトレジスト
技術によ勺、バンプ部プ啄成都のみホトレジスト１０が
開孔されてメッキにより金４が２０〜３０μｍ　の厚さ
で金属バンプとして形成される。金が厚メッキされる過
程で横広がりを生ずる為、バンプ部下方にあらかじめ配
置したスリット７ａの巾に相関のある高さで複数個に分
割した小バンプ間が短絡し、以後は一体となってＩＩＩ
ＩＩＩｌのバンプ電極となる。通常このスリット巾と小
バンプ間が一体化する簡さは１：１の相関がある。例え
ば、２０〜３０μｍ　のバンプ層に対しては、５〜１０
、！ｉｍのスリットを設けて実施する。
この後、メッキ時のマスクとしてのホトレジスト９と１
０とメッキ電極としてのアルミニウム８を除去して、第
２図（ｄ）、　ｔｅｌの様な最終構造が公知の技術で容
易に得られる。
不発明のバンプ部構造を有する半導体装置は、原理的に
―コ複数個の小バンプにより形成され、その上面で１体
化して１つのバンプ電極を構成する。
このバンプ構造のため、生ずる応力がバンプ部内で分散
して、局部的な応力集中を回道し得て、従来型での欠点
を解消した、信頼歴の高い半導体装置を得ることが出来
る。
【図面の簡単な説明】
第１図は従来の半導体装置のバンプ電極部の断面図、第
２図（ａ）〜（Ｃ）は本発明の一実施例に係るバンプ電
極の製造工程について説明する工程途中の半導体基板の
部分断面図、同図（ｄ）、　（ｅ）は同図ｔｃ）に続く
工程後の平面図とそのＡ−Ａｌ析而面である。 １・・・・・・シリコン基板、２・・・・・絶縁膜、３
ａ・・・・チタン膜、３ｂ・・・・・・白金膜、３ｃ　
・・・金膜、４゜１４・・・・・金バンプ、訃・・・・
・電極引出し窓、６，９゜１０・・・・・ホトレジスト
、７・・　・スリットのホトレジスト、７ａ・・・・・
スリット、８・・・・・〆・ンキ用７　／１．、　：電
極。

Claims (1)

    【特許請求の範囲】
  1. バンプ電極の設けられた半導体基板を有する半導体装置
    において、前記バンプ電極の下層部は複数の小バンプに
    分けられ、上層部で一体化されていることを特徴とする
    半導体装置。
JP58115533A 1983-06-27 1983-06-27 半導体装置 Pending JPS607758A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58115533A JPS607758A (ja) 1983-06-27 1983-06-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58115533A JPS607758A (ja) 1983-06-27 1983-06-27 半導体装置

Publications (1)

Publication Number Publication Date
JPS607758A true JPS607758A (ja) 1985-01-16

Family

ID=14664884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58115533A Pending JPS607758A (ja) 1983-06-27 1983-06-27 半導体装置

Country Status (1)

Country Link
JP (1) JPS607758A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477087A (en) * 1992-03-03 1995-12-19 Matsushita Electric Industrial Co., Ltd. Bump electrode for connecting electronic components
WO2002001637A3 (en) * 2000-06-28 2002-09-26 Intel Corp Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs
US6803664B2 (en) * 2001-04-27 2004-10-12 Shinko Electric Industries Co., Ltd. Semiconductor package
US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
JP2007289067A (ja) * 2006-04-25 2007-11-08 Shimano Inc 穂先竿
JP2009240179A (ja) * 2008-03-28 2009-10-22 Daiwa Seiko Inc 穂先竿
EP2447994A3 (en) * 2010-10-27 2018-01-24 Aisin Aw Co., Ltd. Electronic component and electronic device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120683A (en) * 1976-03-31 1977-10-11 Licentia Gmbh Method of making multiilayered metalic electrodes for semiconductor elements
JPS5485671A (en) * 1977-12-20 1979-07-07 Matsushita Electric Ind Co Ltd Semiconductor device
JPS57106056A (en) * 1980-12-23 1982-07-01 Mitsubishi Electric Corp Electrode structural body of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120683A (en) * 1976-03-31 1977-10-11 Licentia Gmbh Method of making multiilayered metalic electrodes for semiconductor elements
JPS5485671A (en) * 1977-12-20 1979-07-07 Matsushita Electric Ind Co Ltd Semiconductor device
JPS57106056A (en) * 1980-12-23 1982-07-01 Mitsubishi Electric Corp Electrode structural body of semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477087A (en) * 1992-03-03 1995-12-19 Matsushita Electric Industrial Co., Ltd. Bump electrode for connecting electronic components
WO2002001637A3 (en) * 2000-06-28 2002-09-26 Intel Corp Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs
US7033923B2 (en) 2000-06-28 2006-04-25 Intel Corporation Method of forming segmented ball limiting metallurgy
US7034402B1 (en) 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US6803664B2 (en) * 2001-04-27 2004-10-12 Shinko Electric Industries Co., Ltd. Semiconductor package
US6835597B2 (en) 2001-04-27 2004-12-28 Shinko Electric Industries Co., Ltd. Semiconductor package
KR100896026B1 (ko) * 2001-04-27 2009-05-11 신꼬오덴기 고교 가부시키가이샤 반도체 패키지
US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
US7208402B2 (en) 2003-12-17 2007-04-24 Intel Corporation Method and apparatus for improved power routing
JP2007289067A (ja) * 2006-04-25 2007-11-08 Shimano Inc 穂先竿
JP2009240179A (ja) * 2008-03-28 2009-10-22 Daiwa Seiko Inc 穂先竿
EP2447994A3 (en) * 2010-10-27 2018-01-24 Aisin Aw Co., Ltd. Electronic component and electronic device

Similar Documents

Publication Publication Date Title
US5226232A (en) Method for forming a conductive pattern on an integrated circuit
US5707894A (en) Bonding pad structure and method thereof
US5310699A (en) Method of manufacturing a bump electrode
JPS607758A (ja) 半導体装置
JP2622156B2 (ja) 集積回路パッド用の接触方法とその構造
JP3206243B2 (ja) ボンディングパッド及びその形成方法
JP2697592B2 (ja) 半導体装置のパッド構造
JPH0442957A (ja) 半導体集積回路装置の製造方法
JP2001176966A (ja) 半導体装置
JP2679388B2 (ja) 半導体装置の製造方法
JPH03101233A (ja) 電極構造及びその製造方法
JPH04278542A (ja) 半導体装置及びその製造方法
JPS6247139A (ja) 転写バンプ基板の形成方法
JPS621249A (ja) 半導体装置
JPH0224376B2 (ja)
GB2244176A (en) Method and apparatus for forming a conductive pattern on an integrated circuit
JPH0645336A (ja) 半導体装置の製造方法
JPH02159033A (ja) 半導体装置
JPH03209823A (ja) 樹脂封止型半導体装置
JPH03132036A (ja) 半導体装置の製造方法
JPS6232636A (ja) 半導体装置
JPH0732157B2 (ja) 半導体装置およびその製造方法
JPH0432235A (ja) バンプ電極の形成方法
JPH02231735A (ja) 半導体装置
JPH02265245A (ja) 半導体装置