JPS6070742A - マスタ・スライス型半導体装置 - Google Patents

マスタ・スライス型半導体装置

Info

Publication number
JPS6070742A
JPS6070742A JP58178591A JP17859183A JPS6070742A JP S6070742 A JPS6070742 A JP S6070742A JP 58178591 A JP58178591 A JP 58178591A JP 17859183 A JP17859183 A JP 17859183A JP S6070742 A JPS6070742 A JP S6070742A
Authority
JP
Japan
Prior art keywords
input
output circuit
circuit area
output
bonding pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58178591A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0542823B2 (cs
Inventor
Takashi Saigo
西郷　孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58178591A priority Critical patent/JPS6070742A/ja
Publication of JPS6070742A publication Critical patent/JPS6070742A/ja
Publication of JPH0542823B2 publication Critical patent/JPH0542823B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP58178591A 1983-09-27 1983-09-27 マスタ・スライス型半導体装置 Granted JPS6070742A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58178591A JPS6070742A (ja) 1983-09-27 1983-09-27 マスタ・スライス型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58178591A JPS6070742A (ja) 1983-09-27 1983-09-27 マスタ・スライス型半導体装置

Publications (2)

Publication Number Publication Date
JPS6070742A true JPS6070742A (ja) 1985-04-22
JPH0542823B2 JPH0542823B2 (cs) 1993-06-29

Family

ID=16051136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58178591A Granted JPS6070742A (ja) 1983-09-27 1983-09-27 マスタ・スライス型半導体装置

Country Status (1)

Country Link
JP (1) JPS6070742A (cs)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02180049A (ja) * 1989-01-04 1990-07-12 Nec Corp 半導体装置
JPH0327529A (ja) * 1990-02-23 1991-02-05 Seiko Epson Corp 半導体集積回路装置
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
EP0826243A4 (en) * 1995-05-12 2000-07-19 Sarnoff Corp PROTECTION AGAINST ELECTROSTATIC DISCHARGE FOR A MACROCELL FIELD
WO2006035787A1 (ja) * 2004-09-28 2006-04-06 Kabushiki Kaisha Toshiba 半導体装置
KR20210045403A (ko) * 2018-08-21 2021-04-26 텍사스 인스트루먼츠 인코포레이티드 패드 제한 구성 가능 로직 디바이스

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02180049A (ja) * 1989-01-04 1990-07-12 Nec Corp 半導体装置
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
JPH0327529A (ja) * 1990-02-23 1991-02-05 Seiko Epson Corp 半導体集積回路装置
EP0826243A4 (en) * 1995-05-12 2000-07-19 Sarnoff Corp PROTECTION AGAINST ELECTROSTATIC DISCHARGE FOR A MACROCELL FIELD
WO2006035787A1 (ja) * 2004-09-28 2006-04-06 Kabushiki Kaisha Toshiba 半導体装置
JP2006100436A (ja) * 2004-09-28 2006-04-13 Toshiba Corp 半導体装置
US7550838B2 (en) 2004-09-28 2009-06-23 Kabushiki Kaisha Toshiba Semiconductor device
KR20210045403A (ko) * 2018-08-21 2021-04-26 텍사스 인스트루먼츠 인코포레이티드 패드 제한 구성 가능 로직 디바이스
CN112840452A (zh) * 2018-08-21 2021-05-25 德克萨斯仪器股份有限公司 焊盘受限的可配置逻辑器件
JP2021534592A (ja) * 2018-08-21 2021-12-09 テキサス インスツルメンツ インコーポレイテッド パッド制限構成可能論理デバイス

Also Published As

Publication number Publication date
JPH0542823B2 (cs) 1993-06-29

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