JPS6068448A - 複数計算機システムの共通メモリ制御方式 - Google Patents

複数計算機システムの共通メモリ制御方式

Info

Publication number
JPS6068448A
JPS6068448A JP58174587A JP17458783A JPS6068448A JP S6068448 A JPS6068448 A JP S6068448A JP 58174587 A JP58174587 A JP 58174587A JP 17458783 A JP17458783 A JP 17458783A JP S6068448 A JPS6068448 A JP S6068448A
Authority
JP
Japan
Prior art keywords
memory
bus
signal
common memory
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58174587A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0351017B2 (enExample
Inventor
Akira Hoshino
星野　公
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58174587A priority Critical patent/JPS6068448A/ja
Publication of JPS6068448A publication Critical patent/JPS6068448A/ja
Publication of JPH0351017B2 publication Critical patent/JPH0351017B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP58174587A 1983-09-21 1983-09-21 複数計算機システムの共通メモリ制御方式 Granted JPS6068448A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58174587A JPS6068448A (ja) 1983-09-21 1983-09-21 複数計算機システムの共通メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58174587A JPS6068448A (ja) 1983-09-21 1983-09-21 複数計算機システムの共通メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS6068448A true JPS6068448A (ja) 1985-04-19
JPH0351017B2 JPH0351017B2 (enExample) 1991-08-05

Family

ID=15981164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58174587A Granted JPS6068448A (ja) 1983-09-21 1983-09-21 複数計算機システムの共通メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS6068448A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128341A (ja) * 1985-11-29 1987-06-10 Yokogawa Electric Corp ２ポ−トメモリへのアクセス制御方式
JPS62297962A (ja) * 1986-06-17 1987-12-25 Fujitsu Ltd メモリの共通領域アクセス制御方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128341A (ja) * 1985-11-29 1987-06-10 Yokogawa Electric Corp ２ポ−トメモリへのアクセス制御方式
JPS62297962A (ja) * 1986-06-17 1987-12-25 Fujitsu Ltd メモリの共通領域アクセス制御方式

Also Published As

Publication number Publication date
JPH0351017B2 (enExample) 1991-08-05

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