JPS6013488A - Digital phase servo circuit - Google Patents

Abstract

PURPOSE:To perform a preferable phase servo in a simple structure by detecting a reference pulse and a coming servo pulse from a general time base, and detecting the phase difference by the value of the difference of these times. CONSTITUTION:When a pulse is outputted from a pulse generator 3 provided on a rotational shaft, the counted value of a time base counter 10 is latched to a data latch circuit 11, and when a pulse is outputted from a synchronization generator 23, it is latched to a data latch circuit 24. A central processor 14 inputs the counted value of the circuit 11 to output the difference from the previously inputted counted value as a speed difference. Further, the difference between the counted value of the circuit 11 and the counted value of the circuit 24 is outputted as a phase difference. Then, the value of the deviation between the speed difference, the phase difference and the set value is supplied through a PWM converter 19 to a motor 21.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase servo circuit that performs phase servo using a microprocessor.

Background Art and its Problems For example, in a recording/reproducing apparatus using a rotary head, it is necessary to perform speed servo, phase servo, or capstan speed servo of the drum of the rotary head.

In this case, in the phase servo, conventionally, for example, a counter is reset with a reference pulse, and a clock pulse is counted with each counter, and then one
A servo pulse obtained with each rotation is detected, and counting is stopped at this pulse, and control is performed so that the counted value at this time becomes a predetermined value.

However, when performing such servo, a dedicated counter is required for this phase servo. In order to increase the accuracy of the servo, a large circuit of, for example, 16 bits or more is used for the counter, and for this reason, if multiple speed servos are performed in addition to the phase servo as mentioned above, a counter is required for each servo system. This requires an extremely large number of counters, making the circuit large and complex, making it difficult to create a compact device.

OBJECTS OF THE INVENTION In view of these points, it is an object of the present invention to enable good phase servo with a simple configuration.

SUMMARY OF THE INVENTION The present invention has a general-purpose time base, detects the time since 3:11 of the reference pulse from the time base, detects the arrival time of the servo pulse from the time base, and detects the arrival time of the servo pulse from the time base. A digital phase servo circuit that detects a time difference, uses the value of this difference to detect a phase difference of the servo pulse with respect to the reference pulse 1, and performs control so that the value of the difference becomes a predetermined value. According to the method, it is possible to perform good phase servo with a simple configuration.

Embodiment In FIG. 1, the tape T is wound around a rotary head drum (]) rotated by, for example, 6011z, and is transported by a capstan (2). Pulse generators (3) are installed on the rotating shafts of these drums (1) and capstans (2).
L (41 is provided, and the servo pulse signals from these generators (31 and +41 are each waveform shaping circuit +5)
, +6) to the data terminal of the C flip-flop +71181. Further, a clock signal of, for example, 2.81'1llz from the reference oscillator (9) is supplied to the synchronization generation circuit (23) to form a vertical synchronization (reference) pulse of, for example, 6011z. Furthermore, the reference oscillator (9)
Karanori r1 Tsuku Hakugo flip flop +71. (8
It is fed to the clock terminal of No. 1 (Ju) and also to the time base counter of No. 16 (00). The count value of this counter flft1 is the data latch circuit (11)
, (12) and <24>, as well as the flip-flops fil, +81 and the synchronization generation circuit (23
) respectively to the latch circuit (11).

The signal is supplied to the latch control terminals (12) and (24).

These latching times 1//l (11), (12),
The numerical value (24) is supplied to the data bus (13). This data bus (13) is connected to the central processing circuit (CPT) (1
4) Read-only memory (ROM) (15)
, random access memory (RAM) (16) are connected.

Further, an address signal from the CPU (14) is sent to the address bus (17), and this address signal is sent to the ROM (14).
5) It is supplied to the RAM (16) and also to the read control terminals of the launch circuits (11) and (12). Furthermore, flip-flop +71. +8) and the synchronization generation circuit (23) are supplied to the interrupt control circuit (18), and when the discrimination signals corresponding to the respective signals are supplied to the data bus (13), the interrupt control signal is transmitted to the husband. C
It is supplied to the PU (14). Further data bus (13)
The signal from is the PWM conversion circuit (1, 9).

(20), and the address signal from the address bus (17) is supplied to the conversion circuit vpI (19), (20).
is supplied to the input control terminal. And this conversion circuit (
PWM signals from 19) and (20) are supplied to the drum motor (2I) and capstan motor (22), respectively.

Furthermore, FIG. 2 shows a signal flow diagram for the drum motor (21). In the figure, the signal from the pulse generator (3) passes through the waveform shaping circuit (5) to the data latch circuit (
11), and the signal from the synchronization generating circuit (23) is also supplied to the data latch circuit (24), where the count value from the time base counter 00) is latched. In addition, the waveform shaping circuit (5) and the synchronization generation circuit (2)
The signal from 3) is supplied to the interrupt control circuit (I8), and the interrupt control signal is supplied to the CPU (14).When this interrupt control signal is supplied to the CPU (14), the interrupt control signal is supplied to the CPU (14).
4) is a latch circuit (11) at a predetermined timing.
and (24) to take in the latched count value.

Here, the counter Ql counts the reference clock signal, so that the hand value indicates the reference time.

Then, in the CPU (14), the waveform shaping circuit (5
) is supplied, the count value of the launch circuit (11) is fetched in the first step (31), and the generation time of the fetched servo pulse signal is stored in the RAM (16). At the same time, the generation time of the previous pulse signal is read out, and the value of this difference is determined. The value of this difference corresponds to the period of the pulse signal mentioned above.

Next, in step (32), ROM (1
5) The target period value stored in 5) is subtracted. As a result, the value of the error from the target period is detected.

Furthermore, in step (33) this il! The value of the 4-difference is multiplied by the speed gain and stored in the RAM (16).

Also, an interrupt control signal from the synchronization generation circuit (23) is 451. When supplied, the count values of the ζ latch circuits (11) and (24) are captured in the first step (35), and the generation time of the servo pulse signal is subtracted from the generation time of the captured reference pulse. The value of this difference corresponds to the phase difference between the reference pulse and the servo pulse signal.

Next, in step (36), from the value of this phase difference, the ROM is
The value of the phase difference of the target stored in (15) and ζ is subtracted. As a result, the value of the error with respect to the target phase difference is detected.

Further, in step (37), this error value is multiplied by a phase gain and stored in the RAM (16).

The two values stored in this RAM (16) are the step (
310, and the subsequent PWM is added in step (34).
The value range is regulated and output according to the control range of 1/8 (19) conversion times.

The PWM conversion circuit (19) is adapted to obtain a predetermined rotational speed by supplying a predetermined drive current to the motor (21) at a predetermined rate of one revolution of the drum, and 4j to motor (2I) according to the value
Speed and phase servo is performed by controlling the duty of the supplied drive current.

Similarly, the speed servo of the capstan motor (22) is also performed.

Phase servo is performed as shown below, but with this circuit, time can be detected on a time base independent of servo. Therefore, the time base can be shared by multiple servos, and the configuration becomes extremely simple.

In other words, only one counter is required for a plurality of servos, making it possible to create a compact device with a simple circuit.

Furthermore, if the servo pulse signal for phase servo is also used as the servo pulse signal for speed servo as described above, it is sufficient to provide only one latch circuit for the speed servo pulse signal.

Furthermore, if the time difference between the reference pulse and the speed servo pulse signal is sufficiently large, these launch circuits can also be shared.

Note that the reference pulse and the speed servo pulse are generated at times such that they do not occur at the same time when the servo is stable.

In addition, the time base can also be used for reel motors, etc.
It can also be used for general purposes such as lighting up displays.

In addition, the value of the counter (I[ll is approximately 7611 in the above example)
Although it returns to 0 at z, an appropriate period and phase difference can be obtained by ignoring the borrow output during subtraction.

In addition, at startup, etc., the machine is placed a predetermined number of times in a certain period of time.
By not processing until the second side is entered, malfunctions during low speed rotation are prevented.

Furthermore, these processes may be incorporated as part of the main routine instead of as an interrupt.

Furthermore, flip-flops (71, +81 are counters (+
This is provided to avoid the change in the value of 111.

Further, the PWM conversion circuits (1!11) and (20) may be DA conversion circuits.

Furthermore, in the above-described circuit, by rewriting the target value stored in the ROM (15), servo can be applied to any desired value, and the circuit can be used as a general-purpose circuit.

Effects of the Invention According to the present invention, good phase servo can be performed with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an example of the present invention, and FIG. 2 is a diagram for explaining the same. +11 is the rotating head drum, (2) is the capstan, (
3). (4) is a pulse generator, +51. (61 is a waveform shaping circuit, 001 is a time base counter, (23) is a synchronization generation circuit, (11), (12), (24) are data latch circuits, (14) is a central processing circuit, (15) is a lead Only memory, (16) is random access memory,
(18) is an interrupt control circuit, (19) and (20) are PW
M conversion circuit, (21) is a drum motor, and (22) is a capstan motor. 0 Fig. 1 L 2 2 4 ” / 3 I 14 6 ri I 5 6 8 12 324 6 4 /θ IA ' 211 L-1□□--hJI If

Claims (1)

[Claims] It has a general-purpose time base, detects the time of arrival of the reference pulse from the above time base, detects the time of arrival of the servo pulse from the above time base, calculates the difference between these times, and uses the value of this difference. A digital phase servo circuit that detects a phase difference between the servo pulse and the reference pulse and performs control so that the value of the difference becomes a predetermined value.