JPS62144209A - Digital phase comparison method - Google Patents

Abstract

PURPOSE:To increase the loop gain of a phase control system by obtaining the arriving time intervals of reference signals to convert them into the time intervals of the frequencies of the PG signals obtained by a rotary phase detector PG and calculating the arriving time point of the reference signal to define the difference between both arriving time points as a phase difference. CONSTITUTION:A digital phase comparator of a VTR, etc., consists of a 1/4 divider 21, a triple multiplier 22, a sawtooth wave generator 23 and a sample holding circuit 24. A rotary head drum 26 is driven and controlled by a speed control circuit 25. The rotary phase is detected by a detector 27 and supplied to the circuit 24. Then the generator 23 is reset by the signal obtained by dividing the vertical synchronizing signal by the divider 21 and multiplying it through the multiplier 22. Thus the sawtooth waves are obtained. These sawtooth waves are sampled/held by the PG signal sent from the detector 27 and the phase error value is obtained. This error value is sent to the circuit 25 for modulation of the speed reference signal. Thus it is possible to perform the phase comparison with the frequency of the PG signal, as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a method for detecting a phase shift between two signals, and can be used, for example, to control the rotational phase of a magnetic head in a rotary head type VTR. It is something.

Conventional technology As a method of recording video signals on magnetic tape.

Rotating head helical scan VTRs are widely used.
For example, VH8 system vTn, 8mi! J video system VTR
and so on. These formats are basically the 7th
As shown in the figure, two video heads B are mounted on the rotating head drum To at an angle of 180°, and the magnetic tape 7 is mounted on the rotating head drum To.
1 is wound diagonally around a rotating head drum To to record video signals. The rotation of the rotary head drum 7o is controlled so that one scan of each head A, H corresponds to one field of the television screen. When the video signal is recorded in this way, the recording pattern on the magnetic tape 71 is the ninth
The result will be as shown in the figure. That is, the head scans from the lower right to the upper left on the tape surface. Also VT
In the case of R, the vertical synchronization signal (hereinafter abbreviated as VS7nO) is
The rotary head drum 70 is controlled so that recording is performed immediately after the scanning start point. For example, in the 8 mm video standard, the period from head switching to vsync is recorded as eH (H is the horizontal synchronization signal interval).

FIG. 10 is a timing waveform diagram showing a phase comparison method when the rotary head drum 70 shown in FIG. 7 is used, and FIG. 12 is a block diagram similarly performing rotational phase control.

In FIG. 12, VS7nC is input to the bar frequency divider circuit 121, and the frequency becomes the frequency divider. The frequency was divided into 87nC
Otherwise, reset the sawtooth generator 122. That is, a sawtooth waveform synchronized by 87nC is generated. This sawtooth waveform is generated from a PG multiplied signal obtained from a rotational phase detector (PG) 126 attached to a rotary head drum motor 125. Sample and bold, input the obtained value to the speed control circuit 124,
Modulate the speed reference. As a result, the rotary head drum 7° rotates in synchronization with the vsync obtained by dividing the rod frequency.

Further, referring to the signal waveform in FIG. 10, 57nO is divided to create μvsync, and the sawtooth wave is reset at the rising edge of the VVsync signal.Meanwhile, the sawtooth wave is sampled and bolded from the PG multiplied signal.

PG multiplication signal Normally, the slope part of the sawtooth wave is sampled and held, so if the PG multiplication signal is delayed, the hold value becomes large, and when the PG multiplication signal is advanced, the hold value becomes small, and as a result, the AVsync and PG This means that a double signal phase comparison is being performed.

In recent years, in order to downsize VTRs, VTRs have been considered that have the same standard, that is, the same recording magnetization locus, but different rotary head drum diameters. For example, as shown in Fig. 8, the diameter of the drum is 275mm, the tape is wound around the corner at 270°, and there are 4 heads, B,
G and D are arranged every 900, and the drum rotation speed is set to 3
By doubling z and performing recording by sequentially switching over the four heads A, B, C, and D, exactly the same recorded magnetization locus as in the conventional method can be obtained. That is, approximately 6 of V1!7TIC
0Hz, the conventional rotating head drum 70 has a frequency of 1800Hz.
The small diameter rotary head drum 80 shown in FIG.

FIGS. 11 and 13 are timing diagrams and block diagrams of a conventional method for performing phase control on such a small diameter drum. In the case of a small diameter drum, the controlled signal is a PG multiplied signal of 4rsHz, and the vsyn of 60
Since it is not possible to perform a direct phase comparison with c, the phase comparison is performed after converting to the greatest common divisor of 1 sHz. That is, in FIG. 13, VS7nC is divided by 1z4 by a 1z4 frequency divider 131 to obtain 16) 1z. The sawtooth wave generator 132 is reset by this 1z4-divided vsync. That is, a sawtooth wave synchronized with vsync which is frequency-divided by 1z4 is generated. On the other hand, the PO multiplied signal obtained from the PG 136 attached to the rotary head drum 8o is divided by 175 by a 115 frequency divider 138 to obtain 1611z. A sawtooth wave is sampled and held from this frequency-divided PG multiplied signal, and the speed reference in the speed control circuit 134 is modulated based on the hold value. This allows phase control to be applied to the small diameter rotary head drum 80.

FIG. 11 is a waveform diagram showing the phase comparison principle.

Divide vsync by 1z4 to get '/4 Vsync,
``Reset the sawtooth wave by the rise of /4Vsync. - On the other hand, divide the pc signal by 3'' /s P G
The sawtooth wave is sampled and held according to the fall of j/sPG, and a phase error signal is obtained. That is, the rotational phase of the rotary head drum 8o is monitored using a frequency that is 1/4 of the vsync frequency (frequency of the PG multiplied signal 175).

Problems to be Solved by the Invention When using a small-diameter rotating head drum, the PQ multiplication signal,
With vsync, direct phase comparison cannot be performed unless the frequencies match, so each signal is frequency-divided to match the frequencies, and phase comparison is performed at a lower frequency. That is, the sampling frequency in the phase control system is lowered. However, in control systems, when the sampling frequency is lowered, control performance often deteriorates. FIG. 14 shows the general form of a sample and hold circuit. The input/output characteristics (frequency characteristics) in this circuit are as follows, when the frequency of the sampling pulse is fs:
The result is as shown in FIG. That is, the gain characteristic is approximately odB when the input frequency is low, but as it approaches the sampling frequency fs, the gain drops rapidly. On the other hand, the phase stability lags in proportion to the frequency, and becomes -π (rad) at the sampling frequency fs. Since the control used in the present invention is a pulse system, such sample and hold is essential. By the way, since sample and hold causes a phase delay, it becomes an element that tends to become unstable as a control system.

In particular, when the sampling frequency is lowered, the phase delay increases from low frequency bands, making it difficult to ensure sufficient control performance. That is, when the loop gain of the control system is increased, it often becomes unstable when the sampling frequency is low. As a result, suppression of disturbances is also reduced.

Furthermore, equipment using a small-diameter rotating head drum can be
Since there are many TRs, it is susceptible to disturbances such as mechanical vibrations, and ensuring control performance is particularly important, and the above-mentioned problems are serious.

Means for Solving the Problems In the present invention, in order to solve the above problems, there are provided means for detecting the arrival time of a reference signal, and means for detecting the arrival time of a PG multiplied signal, which is a controlled signal.

A reference signal that has a sequentially programmable calculation means such as a microcomputer, calculates the arrival time interval of the reference signal, converts the determined time interval to a time interval of the frequency of the PC signal, and converts the frequency of 5 times using the converted time interval. A time difference between the calculated time and the arrival time of the PG multiplied signal is defined as a phase difference.

Effects The configuration of the present invention described above includes means for detecting the arrival time of 57nC and means for detecting the arrival time of the PC signal, and the calculation means calculates VS7n from the generation time interval of VS7nC.
Find the period of C and multiply that value by 415 to virtually '/4
``87nC, predict the generation time of 5/4 vsync, calculate the difference between the predicted generation time of '/4 vsync and the PG double signal generation time, and use it as the phase difference.'' Since the reference signal is a phase-9 frequency co-stable signal, even if a signal delayed from the reference signal is generated in this way, it will not become a delay element in the control system and will not degrade performance.

As a result, phase comparison can be performed using the PG multiple signal frequency without frequency division of the PG multiple signal.

Embodiment FIG. 1 relates to an embodiment of the present invention, in which V divided by 3/4 is
This is a waveform diagram when phase comparison is performed using S7nO and a PG multiplied signal, and FIG. 2 is a block diagram showing a specific configuration in that case. In Figure 2, vsync is set to 1/
The frequency is divided into 1/4 by the 4 frequency divider 21. Next, the divided VS
7nC is tripled by the tripler 22, '/a Vsy
Get nc. (The specific method of creating '/a Vsync will be described later.) With this 3/a Vsync, the 1 gigimeter wave generator 23 is reset, and '/4 vsync
Obtain a sawtooth wave synchronized with . Next, this sawtooth wave is sampled and held using a signal from P(r27) attached to the rotating head drum. This held value becomes a phase error value and is sent to the speed control circuit 26 to modulate the speed reference signal. Thereby, phase comparison can be performed up to 1 of the PG multiplied signal frequency, and the sampling frequency can be kept high.

FIG. 3 is a block diagram showing a specific configuration of the phase comparator in this embodiment. Counter 3o to get time reference
Accordingly, the arrival times of the signals from the 87nC and PG times signals are latched in the latches 31 and 32 in the form of the value of the counter 3o. Using the arrival times of these two signals, a phase comparison is performed by arithmetic processing.

First, using FIG. 4, we will explain the principle by which a phase error can be determined by the pulse arrival time difference. The horizontal axis is a time axis, and although there is no absolute standard (for example, what year in the Western calendar), it is assumed to have relative precision. When the reference signal enters at time t1 and the controlled signal enters at time t2, the difference in arrival time between the two signals is t2-tl. Since both signals have the same frequency, 1
The time difference t2-t is proportional to the phase difference. Therefore, by subtracting the reference phase difference tr6f, the phase error can be obtained, and a phase comparator can be constructed.

However, in the case of the present invention, since the frequencies of the PG multiplied signals 71g7no are different, the microcomputer 33 in FIG. 3 performs the processing shown in FIGS. 6 and 6.

FIG. 6 is a flowchart showing the processing performed when the microcomputer 33 detects the Vsync signal. First, in process 60, variable k (actually memory)
Add 1 to the content of This counts the number of vsyncs. Next, in process 61, the second time “!!7n
The interval between the time O and the four previous vsync times, that is, the period T for four cycles is determined. Next, in process s2,
Check the current count value k of vsync and check whether it is a multiple of 40. If k is a multiple of 4, proceed to process 63 and set 4.
If it is not a multiple of , the process proceeds to step 66. First, in process 63.

Divide 4 times the period T by 3 to find a period DS of 415.

Next, in process 54, the current time Tk is set to the current 5/
4 Let Vsync's arrival time Sj be, add DS to Sj, and find the next "/4 Vsync's arrival time Sj+1.

Add DS to Sj+1, then the next S/a Vsync
Find the arrival time Sj+z. Next, the process proceeds to process 69, where the cycle T four times the current cycle is transferred to another variable T', preparations are made for the next process, and the process ends. Further, in process 66, it is checked whether the current four times the period T and the previous four times the period T' are the same. If they are the same, the process proceeds to process 69; if not, the process proceeds to process 66. In process 66, the difference DT between the current quadruple period T and the previous quadruple period T' is determined. Next, in process 6T, the difference DT is divided by 3, and the arrival time S of '/4 Vsync obtained by the previous time] + 1 +
``3 + 2. Then, on the 6th day of processing, the next arrival time Sj+t, Sj+2
Correct each by nss. The process then proceeds to process 69, where the next preparation is made and the process ends. In Figure 5, 53.
64 process is to create 3/4vsync, and 5
6, 66.

67.58 is a process for 3/a vsync to immediately follow up even if vsync changes midway.

FIG. 6 is a flowchart showing the processing when a PG multiplied signal is input. First, in process 61, 1 is added to the contents of variable j. This is a PG multiplied signal count. Next, in process 62, the current PC, signal arrival time tj
and the corresponding 3/'4vsyn.

The time difference from the arrival time Sj is determined and set as the phase difference P. Next, in process 63, the phase error PIC is determined by determining the difference between the phase difference P and the reference phase difference Praf, and the process ends.

The above is the processing content of the microcomputer 33 shown in FIG. The phase error signal thus obtained is sent through the D/MU converter 34 to the speed control circuit 36 of the rotary head drum motor 36 to modulate the speed reference and provide phase control.

In addition, in the present invention, although there is a concern about the accuracy of calculation,
The resolution of time measurement by time base counter 3o is
It has the same performance as the conventional two-head rotary drum, and if the calculation accuracy is up to 1/s of the resolution of the counter 30 during calculations, the same performance as the conventional two-head rotary drum can be secured. There are no problems in implementation and it is easy to realize.

Further, in this embodiment, the case where the frequency ratio between the reference signal and the controlled signal is 4:3 is explained, but the frequency ratio may be any integer, and the range of application is wide.

In addition, in the embodiment of the present invention, the rotational speed of the rotary head drum is controlled outside the microcomputer, but it is controlled based on the arrival time of the speed pulse (from a frequency generator, etc.) with a common time pace. It is also possible to time-divisionally process the speed control at the same time, resulting in an even greater effect.

Effects of the Invention As stated above, the present invention allows phase comparison to be performed without frequency division even when the frequencies of the two signals to be compared differ, and the sampling frequency of the five-phase control system is not lowered. Therefore, the loop gain of the phase control system can be increased and control performance can be ensured, which has great industrial effects.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing phase comparison in an embodiment of the present invention, FIG. 2 is a block circuit diagram showing the configuration of a phase control system in an embodiment of the present invention, and FIG. 3 is a specific configuration of the phase control system. FIG. 4 is a waveform diagram showing the principle of phase comparison shown in FIG. 3, FIG. Figure 7 is a diagram showing the configuration of the rotating head, drum, and tape in a rotating head type VTR, and Figure 8 shows the same recording trajectory as the configuration shown in Figure 7.Rotating head and small diameter drum , a configuration diagram of the tape, FIG. 9 is a recording magnetization pattern diagram, FIG. 10 is a waveform diagram showing phase comparison when using the rotating head drum of FIG. 7, and FIG. 11 is a diagram of the small diameter rotating head drum of FIG. 8. 12 is a block diagram of a phase control circuit when using the rotary head drum of FIG. 7, and FIG. 13 is a waveform diagram showing the conventional phase comparison when using
FIG. 14 is a block diagram of a conventional phase control circuit when the rotating head drum is used, FIG. 14 is a sample-and-hold circuit diagram, and FIG. 16 is a frequency characteristic diagram of the same circuit. 3o...Time base counter, 31.32.
...Latch, 33...Microcomputer, 26゜35.124,134...Speed control circuit, 26゜36, 125, 135...
Rotating head drum, 27, 37, 126, 136
・・・・・・Rotational phase detector. Name of agent: Patent attorney Toshio Nakao and 1 other person
> Figure 4 A standing phase tkA -b-tr-t, rI! J-Figure 5 Figure 6 Figure 7/A U Figure 8 Figure 9 Figure 12 Figure 13 Figure 14 Figure 15

Claims (3)

[Claims] (1) Means having a common time base and detecting the arrival time of the signal using the value of the time base using a phase reference signal, and detecting the arrival time of the signal using the value of the time base using a controlled signal. and sequentially programmable calculation means, the calculation means calculates the arrival time interval of the reference signal, and multiplies the calculated time interval by a frequency ratio between the reference signal and the control target frequency of the controlled signal. , convert it into a time interval of a signal with the same frequency as the controlled signal, calculate the arrival time of the converted reference signal based on the converted interval, and calculate the arrival time of the calculated converted reference signal and the time of the controlled signal. A digital phase comparison method that calculates the time difference between arrival times and uses this time difference as the phase difference. (2) When the frequency ratio between the frequency of the reference signal and the target frequency of the controlled signal is m:n, find the time interval every m times the reference signal arrives, and each time the reference signal arrives m times, 2. The digital phase comparison method according to claim 1, wherein the time at which the frequency-converted reference signal arrives is calculated. (3) If the arrival time of the frequency-converted reference signal is not calculated even if the reference signal arrives, the time interval between the reference signal arrival time m times before and the current reference signal arrival time, and 1
Claim 2: Comparing the same time interval when the reference signal arrived the previous time, dividing the difference between the two time intervals by n, and correcting the arrival time of the frequency-converted reference signal based on the division result. The digital phase comparison method described.