JPS60255079A - Speed detector for motor - Google Patents

Abstract

PURPOSE:To always detect a speed by the prescribed resolution by providing a frequency divider for dividing a high frequency pulse to supply to counting means, and means for stopping counting when the counted value output arrives at the lower limit value of the speed. CONSTITUTION:A high frequency pulse CP (period T1) is divided by a frequency divider 15 (at frequency dividing ratio:T), and a counter 12 counts the pulse by the pulse EP of an encoder. A latch circuit 13 latches the counted output of the counter 12 by a timing signal EN in response to the pulse signal EP and outputs a speed data. When rotating speed set value is multiplied by (n), the frequency dividing ratio N of the divider 15 is altered to N/n. On the other hand, a comparator 16 stops supplying high frequency pulse to the counter 12 when the counted output becomes larger than the speed lower limit set value.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an improvement of a motor rotation speed detection device that detects the rotation speed of an electric motor from the output of a rotation detector such as an encoder installed in the electric motor. .

<Conventional technology> Usually, the speed control system of an electric motor is as shown in FIG.

In FIG. 2, 1 is an electric motor whose drive is controlled by a drive control device H2, 3 is an encoder that outputs a rotational position pulse of the electric motor 1, and 4 is a speed detection device that detects the rotational speed of the electric motor 1 from the output from the encoder 3. and electric motor 1
A control signal is given from the drive control device 2 to the electric motor 1 based on the output V of the speed detection device W14 corresponding to the rotational speed of the motor and the value of the separately set speed setting value S, and the rotational speed of the electric motor 11 is controlled. .

The present invention provides improvements to the speed detection device WI4 in this speed control system.

Next, details of this speed detection device 4 will be specifically explained with reference to FIG.

As shown in this figure, 11 is a timing generation circuit to which the output pulse EP and high frequency pulse CP from the encoder are given, and 12 is a counter that counts this high frequency pulse (CI) and receives a clear signal CL from the timing generation circuit. The circuit 13 is a latch signal EN from the timing generation circuit 11.
A latch circuit 14 is a read-only memory (ROM) that stores a conversion table for converting the latched count output into speed data.

In such a conventional speed detection device, each time the pulse signal EP from the encoder is input to the timing generation circuit 11, the count output of the counting circuit 12 is latched to the latch circuit 13 by the latch signal @EN, and the counting output of the counting circuit 12 is latched by the latch circuit 13. is cleared by the clear signal CL, and the H1 number circuit 12 starts counting high frequency pulses CP. The latch circuit 13 latches the count output of the previous timing, and the count output latched every time the pulse output EP from the encoder is input is proportional to the pulse cycle of the encoder. Also,
In order to convert this latch output into speed data, speed information V of the motor can be obtained via the ROM 14 in which speed data corresponding to the latch output is written.

For example, if the encoder pulse EP is l k Hz, to detect the speed with an accuracy of 1%, I M f
A high frequency pulse of -1z or higher is required.

In this way, the rotational speed of the motor can be detected with the resolution of the high frequency pulses CP for counting.

<Problems to be Solved by the Invention> By the way, speed control of electric motors is often performed over a wide range (for example, from several 1 Q rpm to several 10,100 rpm).
p. This conventional speed detection IA@ cannot maintain uniform resolution for speed settings over such a wide range.

In other words, as the rotational speed of the motor increases and the pulse output of the encoder becomes shorter, the counting output of the counting circuit decreases, and the resolution of speed detection decreases accordingly, making it difficult to control the speed with high precision. cannot be done.

In other words, if we are trying to measure the speed with an accuracy of 1% for a set speed of several 1100 Orpm, we will need 81 number circuits, latch circuits, and ROMs with very large digits for a set speed of several 1 Orpm. Therefore, this is not realistic.

On the other hand, if the rotational speed of the motor is slow and the cycle of the encoder's pulse output is long, the number of sets of high-frequency pulses CP (31-12) may overflow, and in some cases,
The speed may be output as fast even though it is actually slow.

In this way, the conventional 'IAr! The L detection device had the above-mentioned problems.

The purpose of the present invention is to solve the above problems and provide a motor rotation speed detection device that has the same resolution and accurate output no matter what speed range the motor rotates. be.

Means for Solving the Problem> The configuration of the present invention for solving this problem is as follows.

a timing generation circuit to which the output of a rotation detector installed on the motor and high-frequency pulses are supplied; a set counting means for counting high-frequency pulses using the output of the timing generation circuit; and a count value using the output of the timing generation circuit. In a rotational speed detection device that detects the rotational speed of an electric motor by converting the latched count value output into rotational speed information, the high-frequency pulse is divided into B1.
A motor speed detection device comprising: a frequency divider that supplies the output to the counting means, and a comparator that compares the counted value output with the speed before the lower limit and outputs to the counting means an output that causes the counting to be stopped depending on the result of (a). , is.

<Example> Next, a first example of a motor speed detection device embodying the present invention will be described.
It is shown in the figure and explained in detail.

In FIG. 1, parts having the same symbols as those in the conventional example shown in FIG. 3 have the same functions, so a description thereof will be omitted.

The present invention is characterized by the provision of a frequency divider 15 that can set the high frequency pulse CP to an arbitrary frequency division ratio N, and a comparison circuit 16 that compares the output C of the counting circuit 12 and the lower limit value SL of the rotation speed. It is in.

Next, the operation of this embodiment will be explained.

In this device, when detecting the rotational speed of the electric motor,
The high frequency pulse CP is converted into 4 by the output pulse of the encoder.
At this time, if the period of the high-frequency pulse CP is T1, the pulse CP is divided by the frequency divider 15, and if the frequency division ratio is N, the period 12 of the output pulse from the frequency divider 15 is , T2=NT+, and the counting circuit 12 counts pulses of this period. Encoder pulse EP
If the period of is -[E, then the R1 number output C of the counting circuit 12
is given by C=TE/NT+.

Next, when the rotational speed set value is increased by n times, the period TE- of the pulse EP of the F encoder becomes TE-=TE/n, and the count output C of the counting circuit 12 becomes TE/(nNT+). Here, if the frequency division ratio N of the high frequency pulse CP is changed to N/n by the frequency divider 15, the counting output C of the counting circuit 12 becomes the same as the counting output before the speed setting. That is, for any speed setting value, the frequency division ratio of the high frequency pulse CP is changed by the frequency divider 15 according to the setting value, and the divided high frequency pulse CP is counted, so that the frequency pulse CP is always constant. Speed information ■ can be obtained with resolution.

Next, when the rotational speed of the motor decreases and the period of the pulse EP of the encoder increases, the counting circuit 12 is about to overflow. When the count output C becomes larger than the lower limit set value SL, the comparator 16 outputs the logic "0°" from the logic "1°" to the AND gate 17. , counting circuit 12
The supply of the high frequency pulse CP is stopped, and the counting operation is stopped. Therefore, the count output remains at the speed lower limit set value. Then, when the next encoder pulse EP arrives, the g1 number circuit 12 is cleared and becomes ready to start counting again. Note that at this time, the speed lower limit value is latched in the latch circuit 13.

In this way, overflow of the counting circuit can be prevented and erroneous measurements of the rotational speed of the motor can be prevented.

FIG. 4 shows a specific embodiment of the timing generation circuit 4, and its operation will be explained with reference to the timing chart shown in FIG.

In Fig. 4.5, 41 is a flip-flop circuit, and its set terminal S is connected to the encoder pulse EP shown in (, A).
is supplied, and this encoder pulse EP causes "1" to be output (c) from the output terminal Q. (b) is the high frequency pulse CP. This "1°" output (c) is the high frequency pulse CP (b) is supplied to the input terminal of the flip-flop circuit 42, which is supplied to the clock input terminal CP.

This output (c) is taken into the flip circuit 42 by the high frequency pulse CP (b) following the -encoder pulse EP, and is output from the output terminal Q as "1" as shown in (d). is output. At the same time, a "'0" output is output from the output terminal of the flip-flop circuit M42 to the reset terminal R of the flip-flop circuit 41 (E), thereby resetting the flip-flop circuit 41. Furthermore, this output (d) is appropriately delayed by the delay circuit 43 and becomes the output (v). The count output of the counting circuit 12 is latched by the rising edge of this output (to), and when the output (to) is at the '1' level, the counting circuit 12 is cleared by the high frequency clock CP. The counting output can be latched without any influence, and the counting circuit 12 can be reset.

In this manner, the timing generation circuit 11 can output the latch output of the latch circuit 13 and clear the counting circuit 12.

<Effects of the Invention> As described above, according to the motor rotation speed detection device of the present invention, no matter what the rotation speed of the electric motor is,
Speed can always be detected with constant resolution, and
If the cycle of the output pulses of the encoder becomes longer for some reason, the lower limit value of the rotational speed is output, so that erroneous measurements of the rotational speed of the motor can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a motor rotation speed detection device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a motor speed control system, and FIG. 3 is a diagram of a conventional motor rotation speed detection device. FIG. 4 is a circuit diagram showing the timing generation circuit, and FIG. 5 is a timing chart showing the operation of the timing generation circuit. 11... Timing generation circuit, 12... Four counting circuits,
13...Latch circuit, 14...ROM115...
Frequency divider, 16, comparator, 17...AND gate, 41.42...flip-flop circuit, 43...delay circuit. Figure 1 Swamp 2 Figure yp-J3 Figure Swamp 4 Figure Chapter 5

Claims (1)

[Claims] (1) A timing generation circuit to which the output of a rotation detector installed in the electric motor and high-frequency pulses are supplied, a counting means for counting the high-frequency pulses based on the output of the timing generation circuit, and an output of the timing generation circuit. -Therefore, in a rotational speed detection device comprising a latching means for latching the counted value and converting the output of the latched counted value into rotational speed information to detect the rotational speed of the electric motor, the high-frequency pulse is frequency-divided. Motor speed detection characterized by comprising: a frequency divider that supplies the counting means to the counting means; and a comparator that compares the counting output with the speed setting value and gives an output to the set number means that causes the argument to be stopped based on the result. Device.