JPH0827657B2 - Digital servo control circuit - Google Patents

Description

Detailed Description of the Invention

TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital servo control circuit in a digital audio tape recorder (DAT) or the like. Description of Prior Art of the Invention In a DAT or the like, a digital servo is adopted in order to keep the rotation speed of a rotary drum or a capstan constant. FIG. 6 shows a conventional digital servo control circuit. In the figure, 11 is a rotary drum, and a rotation detector 12 generates a rotation detection pulse FG1 according to the rotation cycle of the rotary drum 11 as shown in FIG. 7 (1). In the case of DAT, the rotation speed of the rotating drum is 2000 rotations per minute as standard (1 second per rotation)
33.3 rotations), and the rotation detection pulse FG1 is configured to generate 20 or more rotation detection pulses per rotation, so the frequency of the rotation detection pulse FG1 is about 800 Hz. This rotation detection pulse
FG1 is divided by the frequency divider 13 to generate the enable pulse El shown in FIG. 7 (2). This enable pulse El is supplied to the measurement counter 14 and the load pulse generator 15,
It has the role of activating the counting operation of the measurement counter 14 and setting the generation timing of the load pulse L1 of the load pulse generator 15. The measurement counter 14 is composed of 12 bits, counts the clock signal CKl shown in FIG. 7 (3) while the enable pulse El is "H", and supplies the count value to the phase modulation counter 16. If the frequency of the clock signal CKl is about 2.5 MHz (for example, 2.4576 MHz), one enable period (enable pulse El
Is “H”), the measurement counter 14 sets the clock signal CKl to 3
It will count about 072. Reference numeral 17 is a reference clock generator, which converts the reference clock signal CK2, which is the reference for digital servo operation, to the clock signal C
Create based on Kl

[Fig. 7 (4)]. Since this reference clock signal CK2 is about 19.2 KHz, 24
Although the position is generated, the number of pulses is omitted in FIG. Therefore, in FIG. 7, the time ranges after (1), (2) and (3) do not match. The reference clock signal CK2 is supplied to the load pulse generator 15, and the load pulse generator 15 outputs the reference clock signal CK2 immediately after the enable pulse El falls as the load pulse L1.

[Fig. 7 (6)]. Then, the phase modulation counter 16 presets the lower 7 bits of the measurement counter 14 when the load pulse L1 is supplied, and thereafter counts the clock signal CKl. Further, the measurement counter 14 stops counting when the enable pulse El becomes “L”, and the load pulse L1 and the clock signal CKl are AND gate 1
It is designed to be reset by a signal via 41.

[Fig. 7 (5)]. Reference numeral 18 is a set-reset (SR) latch, which is set at the rising edge of the most significant bit (7th bit) of the phase modulation counter 16 and reset at the falling edge of the reference clock CK2.

[Fig. 7 (8)]. Since the phase modulation counter 16 counts the clock signal CKl of about 2.5MHz, the frequency of the 7th bit is 19.2KHz,

As shown in FIG. 7 (7), the phase is determined by the count value of the measurement counter 14 which has the same frequency as the reference clock signal CK2 and is preset when the load pulse L1 is supplied. Therefore, if the rotation speed of the rotating drum 11 becomes faster, the count value of the measurement counter 14 becomes smaller, and it takes time from the presetting in the phase modulation counter 16 until the 7th bit thereof rises, so that the phase is delayed and the rotating drum If the rotation speed of 11 becomes slower, on the contrary, the phase of the output waveform of the 7th bit of the phase modulation counter 16 advances. Therefore, the output of the SR latch 18 has a waveform in which the pulse width changes according to the output of the phase modulation counter 16. 19 is a window circuit, which is the upper 6 of the measurement counter 14.
The bit and the load pulse L1 are supplied, and the window gate is applied to the pulse width modulated signal supplied from the SR latch 18 by the value of the upper 6 bits of the measurement counter 14 when the load pulse L1 is applied. That is, in FIG. 7, when the count value of the measurement counter 14 when the normal load pulse L1 is output is 3072B, the upper 6 bits are "110000" and the lower 7 bits are "0000000". . The phase modulation counter 16 counts the clock signal CKl after the lower 7 bits are preset, and the most significant bit rises to 1 after 64 counts. Since the pulse interval of the reference clock signal CK2 is 128 counts, in the normal state, the most significant bit of the phase modulation counter 16 rises at the count up to the center between the pulses. Then, the phase modulation counter 16 outputs the clock signal CKl.
Therefore, since "0000000" to "1111111" are repeatedly counted, there is a possibility that the same rising edge as that of "c" can be obtained even when the measurement counter 14 counts 3072. Then, in reality, it is judged to be normal even though the rotation speed of the rotary drum 11 is largely changed. Therefore, it is necessary to adopt it only when the count value of the measurement counter 14 is around 3072 and to gate the others. Therefore, the window circuit 19 outputs the output waveform of the SR latch 18 as it is as the drum AFC error signal only when the upper 6 bits of the measurement counter 14 are “101111” and “110000”. If it is less than that, it is configured to output "L". On the other hand, 20 is a capstan, 21 is a rotation detector that generates a rotation detection pulse FG2 of the capstan 20, 22 is a frequency divider that divides the rotation detection pulse FG2 and outputs an enable pulse E2, and 23 is an enable pulse E2. Is a measurement counter that counts the clock signal CKl during the period of "H", 24 is a load pulse generator that outputs the reference clock CK2 immediately after the fall of the enable pulse E2 as the load pulse L2, and 231 is the load pulse L2 and the clock signal CKl is input and measurement counter 23
AND gate for supplying a reset signal to 25, 25 is a phase modulation counter that counts the lower 7 bits of the measurement counter 23 by the load pulse L2 and counts the clock signal CKl, 26 is the rising edge of the most significant bit of the phase modulation counter 25 SR latch set by and reset at the falling edge of the reference clock CK2, 27 windows the output of SR latch 26 according to the count value of the upper 6 bits of the measurement counter 23 when the load pulse L2 is applied, This is a window circuit that outputs a capstan AFC error signal, and its operation is the same as that of the drum system described above, so description thereof will be omitted. With the above configuration and operation, the digital servo control circuit expresses changes in the rotational speed of the rotating drum and capstan as changes in the phase, and a pulse width modulated signal of this is expressed as a drum AFC error signal or a capstan AFC error signal. It is what is said. Then, the rotation speed of the motor is controlled according to these error signals. [Problems of Prior Art] In the conventional digital servo control circuit as described above, the drum type measurement counter 14, the phase modulation counter 16,
Capstan type measurement counter 23, phase modulation counter 25
However, in each case, a counter of 6 to 12 bits or more is required in terms of measurement accuracy, and asynchronous counters such as the ripple carry counter have a problem in operation stability. Therefore, as shown in FIG. It must be composed of a synchronous counter that combines a latch and an adder. Therefore, when a large number of counters as described above are used, there is a problem that the circuit scale becomes large. Therefore, it is conceivable that only the latches that make up the synchronous counter are independent and the adder is shared by time division.
In that case, the frequency at which one latch operates drops to 1 / A when A division is performed. Since the frequency of the least significant bit of the phase modulation counter becomes 1 / A, there is a problem that the resolution of the output voltage becomes 1 / A when the frequency of the pulse width modulation signal is kept the same. [Object of the Invention] The present invention has been made in view of the above circumstances, and an object thereof is to provide a digital servo control circuit capable of reducing the circuit scale and improving the resolution of servo control. [Points of the Invention] In order to achieve the above object, the present invention relates to a plurality of synchronous counters for measuring the pulse width of a pulse having a length proportional to the number of revolutions or the phase of the controlled object and performing phase modulation, Only the latch is independent, the adder is time-divisionally shared at the timing of each 1 / A, and the lower bit of the latch operating at the frequency of 1 / A of the fastest frequency is corrected by the counter operating at the fastest frequency. It is characterized by [Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. The same circuits and signals as those in the conventional example are designated by the same reference numerals, and detailed description thereof will be omitted. However, in the present embodiment, since the measurement circuit is time-divisionally driven once every four times, the measured value becomes 1/4 of the case described with reference to FIG. In order to match with, the discussion will proceed assuming that the frequency of each clock is quadrupled. Therefore, the clock signal CK1 is about 9.8 MHz and the reference clock signal CK2 is about 76.8 KHz. This is just for the convenience of explanation, and it is not actually necessary to raise the frequency. In FIG. 1, 11 is a rotary drum, 12 is a rotation detector that generates a rotation detection pulse FG1 for the rotary drum, and 13 is a frequency divider that divides the rotation detection pulse FG1 by two and outputs an enable pulse El. , 17 is a reference clock generator that outputs a reference clock signal CK2 based on the clock signal CKl, 151 is a load pulse generator that outputs a load pulse L11, while 20 is a capstan, 21 is a rotation detection of the capstan Rotation detector generating pulse FG2, 22 is enable signal E2
, 241 is a load pulse generator that generates a load pulse L21. Reference numeral 31 is a time division control counter, which receives the clock signal CKl and the reference clock signal CK2, and divides the pulse width of the reference clock signal CK2 into four as shown in FIG. 2 (5). Output d. The time division pulses a, b, c and d are used for time division control of the main part of the circuit shown in FIG. The time-division pulse c is input to the load pulse generator 151, and the time-division pulse d is input to the load pulse generator 241.
Is the reference clock signal immediately after the enable pulse El falls
The AND output of CK2 and the time division pulse c is used as a load pulse L11, and the load pulse generator 241 uses the AND output of the reference clock signal CK2 and the time division pulse d immediately after the fall of the enable pulse E2 as the load pulse L21. . Reference numeral 32 denotes a drum measurement latch, which is composed of 12 bits and is for counting the clock signal CKl according to the rotation speed of the rotary drum 11, to which the time division pulse a and the load pulse L11 are inputted. Reference numeral 33 denotes a capstan measuring latch, which is also composed of 12 bits and is for counting the clock signal CKl in accordance with the rotation speed of the capstan 20, to which the time division pulse b and the load pulse L21 are inputted. . Reference numeral 34 is a drum phase modulation latch consisting of 5 bits, and 3 to 7 bits of the count value latched by the drum measurement latch 32 are preset. Then, the preset value is phase-modulated and output,
The time-division pulse b and the load pulse L11 are input, and the carry signal of the second bit from the top when the most significant bit of the latch data is "0" is output as the phase modulation signal T1. A capstan phase modulation latch 35 is also composed of 5 bits, and 3 to 7 bits of the capstan measurement latch 33 are preset. Then, the preset value is phase-modulated and output. When the time-division pulse c and the load pulse L21 are input and the most significant bit of the latch data is "0", the carry signal of the second bit from the top is phased. Output as modulated signal T2. 36 is an adder, which is connected to each of the above-mentioned latches 32, 33, 34, 35 via a bus line BL. The adder 36 is for inputting the latch data of the above-mentioned latches 32 to 35, adding 1 and writing again to the respective latches 32 to 35.
When the addition command S from the adder control circuit 37 is "H", the addition operation is performed. The adder control circuit 37 uses the time division pulse a,
b, c, d, enable pulses E1, E2, load pulse L1
1 and L12 are input and an addition command S is output, the details of which are shown in FIG. That is, AND gate 371, 37
The time-division pulses a, b, and
c and d are input, enable pulses E1 and E2 are directly input to the other input ends of the AND gates 371 and 372, and load pulses L11 and L12 are input to the other input ends of the AND gates 373 and 374, respectively, to the inverter 375, Has been entered through 376.
The outputs of the AND gates 371 to 374 are input to the OR gate 378, and the output of the OR gate 378 becomes the addition command S. Reference numeral 38 denotes a drum system lower-order bit corrector, which is composed of a 2-bit counter, and the lower-order 2 bits of the drum measurement latch 32 are set via the bus line BL, and
The clock signal CKl and the load pulse L11 are input.
The lower bit compensator 38 includes the drum measurement latch 32.
Is operated by the time-division pulse a, the operating speed becomes 1/4 of that of the clock signal CKl. This is for correcting this by the clock signal CKl.
The carry output K1 of the lower bit corrector 38 is supplied to the set / reset (SR) latch 39. The SR latch 39 receives the time-division pulse c, the reference clock signal CK2, and the phase modulation signal T1 from the drum phase modulation latch 34, and carries the carry output K1 of the lower bit corrector 38 and the drum phase modulation latch 34. Is set by the AND signal of the phase modulation signal T1 and is reset by the AND signal of the reference clock signal CK2 and the time division pulse c. The output of the SR latch 39 becomes a pulse-width modulated signal PWM1 and is supplied to the window circuit 40. The role of the window circuit 40 is the same as that described as the prior art, and the upper 6 bits of the drum measurement latch 32 are input via the bus line BL. The details are shown in FIG. In FIG. 4, 401 is a decoder, and the upper 6 bits of the drum measuring latch 32 are "10111".
"1" is output to the latch circuit 402 only when "1" and "110000". On the other hand, of the 6 bits supplied from the drum measuring latch 32, the upper 2 bits are input to the AND gate 403, and the AND output is input to the latch 404. Latch 4
The load pulse L11 is input to 02 and 404 as a latch clock, the output of the latch 402 is supplied to the gate 405 as a gate open signal, and the inverter 406
And is supplied as a gate open signal to the gate 407 via. On the other hand, the output PWM1 from the SR latch 39 is input to one input terminal of the OR gate 408 via the gate 405. The output of the latch 404 is input to the other input terminal of the OR gate 408 via the gate 407. The output of the OR gate 408 becomes a drum AFC error signal. 41 is a capstan system lower bit corrector, and the lower 2 bits of the capstan measurement latch 33 are the bus line BL.
The clock signal CKl and the load pulse L21 are also input. This low-order bit corrector 41
Carry output K2 is input to SR latch 42. SR latch
The time division pulse d, the reference clock signal CK2, and the phase modulation signal T2 of the capstan phase modulation latch 35 are input to 42, which is set by the AND signal of the carry signal K2 and the phase modulation signal T2, and the time division pulse d And reference clock signal CK2
Is reset by the AND signal of, and its output is supplied to the window circuit 43 as a pulse-width modulated signal PWM2. The window circuit 43 is a capstan measurement latch.
The upper 6 bits of 33 and the load pulse L21 are input, and the capstan AFC error signal is output. Next, the operation of the digital servo control circuit configured as described above will be described with reference to the time charts of FIGS. The rotation detector 12 detects the rotation of the rotating drum 11, and the
Generates z rotation detection pulse FG1. Divider 12
The frequency is divided and an enable pulse El of about 400 Hz is output. Part of the rotation detection pulse FG1 and the enable pulse El is shown in FIGS. 2 (1) and 2 (2). Further, the reference clock generator 17 generates the reference clock signal CK2 shown in FIG. 4 (4) based on the clock signal CKl shown in FIG. 3 (3). In FIG. 2, there is a 128: 1 relationship between the frequency of the clock signal CKl and the frequency of the reference clock signal CK2, and the time range in the drawing does not match. On the other hand, the time division control circuit 31 generates time division pulses a, b, c, d as shown in FIG. 5 (5) based on the clock signals CKl, CK2. Incidentally, in FIG. 2 (1) and (2), the rotation detection pulse
The timing of the rising edge of FG1 and the falling edge of the enable pulse El are shifted because the frequency divider 13 operates in synchronization with the clock signal CKl. Therefore, the drum measurement latch 32, the capstan measurement latch 33, the drum phase modulation latch 34, and the capstan phase modulation latch 35 share the adder 36 in a time division manner, and each latch is respectively It operates during the period of the time division pulse a, the period of b, the period of c, and the period of d. During the period of the time division pulse a, the drum measurement latch 32 outputs the data latched at the rising edge of the time division pulse a, and latches the data from the adder 36 at the falling edge. At this time, in the adder control circuit 37, since the AND gate 371 is opened, the enable pulse El passes through the AND gate 371 and the OR gate 378, and the add command S is set to “H” only when the enable pulse El is “H”. Will be applied to 36

[Fig. 2 (9)]. Therefore, the content of the drum measuring latch 32 is changed every time the time-division pulse a is applied.
One is added one by one through the BL and the adder 36. Then, when the enable pulse El falls, the load pulse L11 is output from the load pulse generator 151 as shown in FIG. 2 (6), so that the drum measuring latch 36 outputs the load pulse L1.
When 1 is applied, the 3 to 7 bits are output to the drum phase modulation latch 34, and the lower 2 bits are output to the lower bit corrector 38. In the period of the time division pulse b, the capstan measuring latch 33 similarly performs the counting operation during the period in which the enable pulse E2 is "H". In the period of the time-division pulse c, the drum phase modulation latch
34 performs a count operation. When the load pulse L11 is applied, the phase modulation latch 34 reads 3 to 7 bits of the data latched by the drum measurement counter 32 and is preset. Then, every time the time-division pulse c is applied thereafter, the contents thereof are added one by one via the bus line BL and the adder 37. At this time,
Since the adder control circuit 37 opens the AND gate 373 when there is no load pulse L11, the adder 36 is caused to perform the addition operation during the period of the normal time division pulse c, and the addition operation is performed only when the load pulse L11 is output. The data from the drum measurement latch 32 is preset to the drum phase modulation latch 34 without performing the above. When the most significant bit of the drum phase modulation latch 34 is "0", the carry signal of the second bit from the top is the phase modulation signal.
Supplied to SR latch 39 as T1

[Figure 5 (5)]. That is, when the load pulse L11b in FIG. 5 is generated, 5 to 7 bits of the data latched in the drum measurement latch 32 are preset in the drum phase modulation latch 34, and the time division pulse is generated. Each time c is generated, it is incremented by 1, so the count value is "0111.
Considering the timing of changing from “1” to “10000”, it can be seen that it changes depending on the preset value. For example, if the normal count value is 3072 (“110000000000” in binary number, 3 to 7 bits thereof are “00000”), 16 counts will be taken before “00000” changes to “10000”. Drum phase modulation latch 34 at this time
If the rising of the carry signal of the second bit from the top is taken as b, the phase difference of the rising of the carry signal with respect to the waveform of b is the difference in the count value of the drum measuring latch 32, that is, the rotation speed of the rotary drum 11. It corresponds. Therefore, the carry signal of the second bit from the top when the most significant bit of the drum phase modulation latch 34 is "0" is output as the phase modulation signal T1. In FIG. 5, the clock signal CKl is about 9.8 MHz, the time division pulse c
Is about 2.5 MHz and the reference clock signal CK2 is about 76.8 KHz. Therefore, the time range is not matched after (1), (2) and (3). In the period of the time-division pulse d, the capstan phase modulation latch 35 similarly performs the preset operation and the count operation from the capstan measurement latch 33, and the most significant bit from the top 2 is “0”. The bit carry signal is supplied to the SR latch 42 as the phase modulation signal T2. On the other hand, the lower bit corrector 38 presets the lower 2 bits of the drum measuring latch 32 when the load pulse L11 is applied, and thereafter counts the clock signal CKl. Therefore, the carry signal K1 is output every four clock signals CKl as shown in FIG.
It is supplied to the latch 39. The SR latch 39 includes the phase modulation signal T1 from the drum phase modulation latch 34 and the carry signal K1.
Of the reference clock signal CK2 and the falling AND signal of the time division pulse c. Therefore, although the phase modulation signal T1 is converted into a pulse width modulation signal, the drum phase modulation counter 34 performs the addition operation only when the time division pulse c is generated, and therefore the clock signal CKl which is the fastest clock.
Accuracy is 1/4 compared to. Therefore, the 3rd to 7th bits of the data of the drum measurement latch 32 are preset in the drum phase modulation latch 34, and the 1st to 2nd bits are preset in the lower bit corrector 38 to obtain the minimum clock signal CK.
The l counts independently. And this S
In the R latch 39, the phase modulation signal T1 from the drum phase modulation latch 34 and the carry signal from the lower bit corrector 38
If it is set by the AND signal of K1, the same operation as that of the 7-bit counter that counts the clock signal CKl can be obtained. Pulse width modulated signal PWM1 from this SR latch 39
Becomes a drum AFC error signal via the window circuit 40. That is, the upper 6 bits of the drum measurement latch 32 are decoded by the decoder 401, and "101111" and "11000"
Only when it is "0", the output signal "1" is obtained and set in the latch 402 by the load pulse L11. On the other hand, when the upper 2 bits are input to the AND gate 403 and are "11", "1" is set to the other gates, and "0" is set to the latch 404 by the load pulse L11. Therefore, when "1" is set in the latch 402, the gate 405 is opened and the pulse width modulation signal P from the SR latch 39 is set.
WM1 is output as a drum AFC error signal as it is, and when "0" is set in the latch 402, the gate 407 opens and the output of the AND gate 403, that is, "1" when the upper 2 bits are "11", that Other than that, "0" is output as a drum AFC error signal. Therefore, if the count value of the drum measurement latch 32 is 64 counts before and after the reference value 3072, that is, if it is within the range of 3008 to 3135, the pulse width modulation signal PWM1 corresponding to the count value is output as it is, 3008 When it deviates to the lower side, it outputs a "0" signal, and when it deviates to the 3136 or higher side, it outputs a "1" signal. On the other hand, the capstan type lower bit corrector 41, the SR latch 42, and the window circuit 43 have the same operation principle as the drum type, and therefore the description thereof will be omitted. As described above, according to this embodiment, the frequency of the rotation detection pulse FG of the rotary drum is f _FG , and the clock signal CKl is
Is f ₁ , the frequency of the reference clock signal CK ₂ is f ₂ , the number of bits of the drum measurement latch 32 is n, and the number of bits of the drum phase modulation latch 34 + the lower bit compensator 38 is m, then f ₂ = f There is a relationship of ₁ × 2 ^-m , and the wavelength of f _FG is The servo is controlled so that The frequencies of the signals shown in the above embodiment are merely examples, and the frequencies are not limited thereto. Also,
The frequencies of the drum system and the capstan system may be common or independent. Further, in the above embodiment, the rotation speed (frequency) control of the drum and the capstan has been described as an example, but the invention can be applied to the phase control. [Effect of the Invention] As described in detail above, in the digital servo control circuit of the present invention, the multi-bit synchronous counter, which is used in large numbers, has only the latch section independent, the adder is shared by time division, and By correcting the lower bits of the latch operating at the frequency of 1 / A by the counter operating at the highest frequency, the circuit scale can be reduced and the servo control resolution can be improved.

[Brief description of drawings]

1 to 5 show an embodiment of the present invention, FIGS. 6 to 8 show a prior art, and FIG. 1 is a block diagram showing a configuration of a digital servo control circuit of this embodiment. 2 and 5 are time charts for explaining the operation of this embodiment, FIG. 3 is a diagram showing the circuit configuration of the adder control circuit 37 of FIG. 1, and FIG. 4 is of FIG. FIG. 6 is a diagram showing the circuit configuration of the window circuit 40, FIG. 6 is a block diagram showing the configuration of a conventional digital servo control circuit, FIG. 7 is a time chart for explaining the operation of FIG. 6, and FIG. It is a figure which shows the principle of a counter. 11 …… Rotary drum, 12,21 …… Rotation detector 13,22 …… Divider, 151,241 …… Load pulse generator 17 …… Reference clock generator, 20 …… Capstan 31 …… Time division control circuit , 32 …… Latch for drum measurement 33 …… Latch for capstan measurement 34 …… Latch for drum phase modulation 35 …… Latch for capstan phase modulation 36 …… Adder, 37 …… Adder control circuit 38, 41… … Lower-order bit corrector, 39,42 …… SR latch 40,43 …… Window circuit

Claims (1)

[Claims] 1. A servo error is generated by generating a pulse having a length proportional to the number of revolutions or phase of a controlled object, measuring the length of the pulse, phase modulating the measured value, and then pulse width modulating. In a digital servo control circuit for outputting a signal, a means for generating a clock signal of frequency f ₁ , a means for generating A type time-division pulses that are out of phase with each other, and a frequency f ₂ synchronized with this time-division pulse While the means for generating the clock signal of (f ₂ <f ₁ ) and the pulse having the length proportional to the rotational speed or the phase of the controlled object are present, the addition operation is performed at every 1 / A timing. A first latch having an n-bit configuration in which a numerical value indicating the length of is stored, and l bits (l ≦ n−k) excluding the lower k bits among the numerical values stored in the first latch are preset, 1 / A
The second latch having an l-bit configuration for performing the addition operation at each timing of 1 to convert the preset numerical value into the phase modulation signal having the frequency f ₂ and the lower k bits of the numerical value stored in the first latch are A counter that presets and outputs a carry signal by counting a clock signal of frequency f ₁ , a phase modulation signal output from the second latch, a carry signal of the counter, and a clock signal of frequency f ₂ And a means for generating a pulse width modulated signal and a means for outputting this pulse width modulated signal as an error signal. The first and second latches share a bus line and an adder, and the time division is performed. Each addition loop is time-divisionally closed at a timing of 1 / A by a pulse, and is characterized by the relationship of f ₂ = f ₁ × 2- ^{(l + k)} , 2 ^k = A. Do Ijitarusabo control circuit.