JPH0255438A - Simple integration type dpll phase control system - Google Patents

Abstract

PURPOSE:To reduce and simplify a circuit scale by utilizing an output of a readout counter of an elastic memory directly and controlling a phase comparison output. CONSTITUTION:A phase control circuit 2 fetches a phase comparison output PCO of a phase comparator 1 comparing the phase of the 1st stage output Rphi1 of an N stage readout counter 14 of an elastic memory 10A with a phase of the 1st stage output Wphi1 of an N stage write counter 13 based on outputs before and after the 1st stage output Rphi1 of the readout counter 14, that is, the final stage output RphiN and the 2nd stage output Rphi2. In this case, the phase control circuit 2 normally fetches a level L of a phase comparison output PCO by using the output RphiN of the counter 14 and fetches a level H from the output Rphi2 to apply no control, but when the level H of the output PCO is fetched by using the output RphiN, the circuit 2 applies the control of retarding the phase of the DPLL and when a level L of the output PCO is fetched by the output Rphi2, the circuit 2 applies the control of advancing the phase.

Description

[Detailed Description of the Invention] [(Already required)] By comparing the phases of the write clock and read clock of an elastic memory used for data speed conversion, etc., the phase of the read clock generated is digitally controlled in a loop and locked. Regarding the so-called DPLL circuit, which outputs a phase comparison output from the LL circuit, we aim to simplify the digital phase control circuit that integrates the phase comparison output of the LL circuit and outputs a phase lead control signal and a phase lag control signal.
The phase comparison output pco of the output of the phase comparator which compares the phase of the first stage output RφI of the read counter of the stage and the first stage output weak φ1 of the write counter of the N stage is the first stage output Rφ1 of the read counter.
A flip-flop which takes in the final stage output Rφ8 and the second stage output Pφ2 before and after, respectively, and the output of the flip-flop is further divided into two selected from two clocks having a frequency half the frequency of the master clock MSK and a phase difference π. It is equipped with a phase control circuit consisting of a flip-flop that takes in one clock each based on the clock MCK2, and normally the phase control circuit takes in the level "I," of the phase comparison output pco from the final stage output Rφ8 of the read counter. The level of the inverted signal of the output PCO is determined by the two-stage output Pφ2.
11" is taken in and is not controlled, but when the output PCO level "11' is taken in by the final stage output Rφ8, the DI
The configuration is such that the phase delay control is performed on the LL, and when the level "L" of the inverted signal of the output pco is taken in by the second stage output Rφ2, the phase advance control is performed on the DPLL.

[Industrial application field]

The present invention is a digital phase system that digitally loop-controls and locks the phase of the read clock generated by comparing the phases of the write clock and read clock of an elastic memory used for data rate conversion in data communication, etc. Lock loop, so-called Kano LL circuit, especially DP
The present invention relates to simplifying a digital phase control circuit that integrates the phase comparison output of an LL circuit and outputs a phase lead signal and a phase lag signal.

[Conventional technology]

Conventionally, the phase control method when the elastic memory read clock is generated by a DPLL is as shown in the block diagram of FIG. N pieces of write data at low speed. ATA is sequentially written to N stages one by one using N addresses obtained by counting the write clock -CLK by an N stage ring counter 13^, and the written data is written to the DPLL circuit 100A described below. Using the N addresses obtained from the count value of the N-stage ring counter 14A that counts the clock generated by the read clock Rcm, the N addresses are sequentially read out to the N stages in the writing order one stage at a time, and the input N/output 1 is read out. The output is input to the N-1 selector 12A, and the selector 12A selects and outputs the one-man power.

In that case, the phase comparator S of the DPLL circuit 100^
-R latch IA is an N-stage ring counter 13 for writing.
The first stage output -φ1 of A is input to the terminal, and after reset, the first stage output Rφ of the N-stage ring counter 13A for reading.
1 to the S terminal, compare the phase difference between the two and output P.
It is outputted as CO from the 0 output terminal and inputted to, for example, an up/down counter 2A. The amplifier down counter 2^ receives the required read clock R to the elastic memory 10.
The output of the fixed oscillator 5A that oscillates at a fixed frequency 2nf, which is an integral multiple of the frequency f of CLK, is input to the CK terminal as the master clock MCK and counted, and if the counting result exceeds a preset value, the phase advances. The carry CO of the control pulse is outputted, and the borrow BR of the phase delay control pulse is outputted when the dark value is not reached.
Send to A. OR circuit 3A takes the OR of both cities, and 2
The output of the frequency divided by two by the frequency divider 48 is used as the clock selection signal S to control the 2-1 selector 9A.

The 2-1 selector 98 inverts the master clock MCK output from the fixed oscillator 5A using an inverter 6A, and then divides the frequency by 2 using a frequency divider 7A. The output O is connected to an AND circuit 818 and an AND circuit 8, respectively.
At 2A, the two outputs of the 0-phase output CKO and the π-phase output CK π which are AND-processed with the master clock MCK are input.
One of them is selected by the output S of the frequency divider 4A, but at all times, the selection signal S obtained by dividing the carry CO of the phase advance control pulse of the up/down counter 2^ by 2 is used to select the π-phase output. CKπ is selected and outputted to the output AND circuit 10A as a master clock MCK 2 whose frequency is divided by two.

Then, the OR circuit 3A is the borrow B of the phase delay control pulse.
If R is output, the corresponding Poroa Bl? The AND circuit 10 outputs a signal inverted by the inverter 11A and a master clock MCK 2 obtained by dividing the frequency of the π-phase output CK π by 2.
A pulse corresponding to the π-phase output CK π of the output when the phase is advanced is removed and outputted to the n frequency divider 2OA as an output when the phase is delayed. And n of the output of n frequency divider 2OA
A frequency-divided signal, that is, a clock with a frequency f obtained by dividing the original master clock MCK by 2n, is sent to the elastic memory 10A.
The read data RDA is supplied as the required read clock Rcm to the N-stage ring counter 13A for reading to generate a read address, and the read data RDA is phase-locked to the mask clock MCK by the selector 12A to the elastic memory 10.
It is configured to obtain TA.

[Problem to be solved by the invention]

As described above, in the conventional DPLL phase control method, the first stage output H to the counter 13 is based on the write clock WC1 of the low-speed data W DATQ input to the elastic memory January peak.
The phase difference between φ1 and the first stage output Rφ1 of the counter 14A of the read clock RC11 is determined by the S, -R latch IA that operates at the rising edge, and the read clock is determined by the phase comparison output pco at the 0 output end of the S-R latch IA. RCLK
The phase control of P is performed by DPLL, that is, the phase comparison output P
The master clock MSN is counted and integrated by the CO using, for example, an amplifier down counter 2A as an integrator circuit, and the phase is controlled to advance/delay based on the result of determining whether it is large or small with respect to a predetermined dark value. In this case, the up/down counter 2A as an integrating circuit is an elastic memory 10A.
The time width of each of the level "L" of the comparison output pco at the constant cycle 1/f of the predetermined read clock of is counted, but the master clock MCK whose count pulse width is 1/2fn is counted. Therefore, there is a problem that the hardware scale for counting increases.Also, although not shown in the figure, when control is performed by performing integration using an analog time constant CH that normally handles high-speed data as an integrating circuit for low-speed data. However, there is a problem in that the time constant CR becomes large and its setting is difficult.

The present invention is a simplified integral type DP that is a simplified digital type integral circuit that is normally used as a low-speed data integral circuit.
The objective is to provide an LL phase control method.

[Means to solve the problem]

This problem consists of the first stage output Rφ1 of the N stage read counter and the first stage output Rφ1 of the N stage write counter of the elastic memory.
A flip-flop which takes in the phase comparison output pco of the output of the phase comparator which compares the phase of φ1 with the final stage output Rφ8 and second stage output Rφ2 before and after the first stage output Rφ1 of the read counter, and further outputs the output of the flip-flop. Divide-by-2 clock MCK 2 selected from two clocks with a frequency that is half the frequency of the master clock MSK and a phase difference of π
The phase control circuit is provided with a phase control circuit consisting of a flip-flop that takes in one clock each, and normally the phase control circuit takes in the level "L" of the phase comparison output pco by the final stage output Rφ8 of the read counter, and the second stage output Rφ2. When the level "H" of the inverted signal of the output pco is taken in by the final stage output Rφ8 and the level "P11" of the output pco is taken in by the final stage output Rφ8, phase delay control is performed on DI'LL, and the second stage output Rφ2 The D of the simple integral formula of the present invention is configured so that when the level "L" of the inverted signal of the output pco is taken in, the phase of the DPLL is advanced and controlled.
This problem can be solved using the PLL phase control method.

In the principle diagram of FIG. 1 showing the configuration of the simple integral type DPLL phase control system of the present invention, 10 is an elastic memory that does not read written data in the order in which it was written using a separate clock, and has a latch 11 and a selector 1.
Consists of 2.

11 is a launch for writing and temporarily storing N pieces of write data DATA using the output of the N-stage write counter 13 that counts the write clock Wcm as an address.

Reference numeral 12 denotes a selector that reads and inputs the data written in the latch 11 in the order of writing using the output of the N-stage read counter 14 that counts another read clock RC1l as a selection signal S, and selects one of them.

I3 is an N-stage write counter that counts the write clock WCLX.

14 is an N-stage read output rank that counts the read clock RCLK.

100 is a digital phase-locked loop DPLL.

1 is the first stage output Rφ1 of the N-stage read counter 14 that generates the selection signal S of the selector 12 of the elastic memory 10.
This is a phase comparator that compares the phases at each rising edge of the output Wφ1 of the N-stage write counter that creates the write address of the latch 11 and outputs a phase comparison output pco.

2 converts the sign-inverted output of the comparison output pco of the phase comparator 1 by the inverter 25 to the first stage output Rφ1 of the read counter 14.
a flip-flop 22 that takes in the second stage output Rφ2 one clock later than the second stage; a flip-flop 21 that takes in the output PCO of the phase comparator 1 as it is at the final stage output edge φ8 one clock earlier; and the flip-flop 22.2.
It consists of flip-flops 24 and 23 that take in the respective Ω outputs of 1 and 2 using a 2-frequency divided clock MCJ2, which is obtained by dividing the master clock MCK by 2 (to be described later), and generates a phase advance signal CO or a phase delay signal CO from the comparison output pco of the phase comparator. This is a phase control circuit that obtains the signal BR.

Reference numeral 3 denotes an OR gate which inputs the phase advance signal CO and the phase delay signal BR output from the phase control circuit 2 and performs OR processing.

4 is a frequency divider by two that divides the frequency of the output of the OR gate 3 into two.

5 is a frequency 2nf that is an integral multiple of 2n of the frequency f of the required read clock RCLK that is supplied to the read counter 14 that generates the selection signal S of the selector 12 of the elastic memory 10.
6 is a master clock generator that generates a master clock MSN, and 6 is a sign inverter.

Reference numeral 7 denotes a frequency divider by 2 which inverts the sign of the master clock MSK output from the master clock generator 5 and inputs it to the sign inverter 6 to divide the frequency by two.

8L82 gates the output 1 inverted output Q of the frequency divider by using the master clock MSK output from the master clock generator 5 so that the frequency is 1/2 of the frequency of the master clock MSN and the phase difference is Clock CK where is π
This is an AND gate that outputs O and clock CKπ.

9 is the clock CKO of the output of Antogame 1-8L82
and the clock CKπ, select one of them using the output of the 2-frequency divider 4 as the selection signal S, and output the 2-divided clock MSK 2 with a frequency nf whose frequency is 172 of the frequency 2nf of the master clock MSK. It is a selector.

Reference numeral 10 denotes an output gate that performs AND processing on the 2-frequency divided clock MSK 2 output from the selector 9 using a sign-inverted signal from the inverter 11 of the phase delayed signal BR output from the phase control circuit 2.

20 divides the frequency nf of the output of the output gate 10 by 2 to obtain a clock with the desired frequency f.
It is a frequency divider.

Normally, in the phase control circuit 2, the flip-flop 21 takes in the level "L" of the phase comparison output PCO, the flip-flop 22 takes in the inverted level "■", and the flip-flop 23 advances the phase of the signal CO. The flip-flop 24 outputs the phase delayed signal BR and becomes uncontrolled. At that time, the selector 9 selects a repetition frequency of 172 times nf of the frequency 2nf of the master clock MSK and 1 of the master clock MSN. The configuration is such that a divided-by-2 clock M (J 2) with an advanced phase to which J 2 pulses are added is selected.

[Effect]

The phase comparator 1 outputs the first stage output Rφ1 of the N-stage read counter 14 that generates the selection signal S of the selector 12 of the elastic memory January 0, and the first stage output Wφ1 of the N-stage write counter that generates the write address of the latch 11. The phases are compared at each rising edge of PCO, and the comparison output PCO is output to the phase control circuit 2.

The flip-flop 21 of the phase control circuit 2 inputs the comparison output PCO from the phase comparator 1 as it is to the D terminal, and outputs the final stage output RφN one clock before the first stage output Rφ1 of the N-stage read counter 14 to the CK terminal. The output is input to the D terminal of the flip-flop 23. Then, by the 2-frequency divided clock MCK 2 inputted to the CK terminal of the flip-flop 23, 1 of the 2-frequency divided clock MCI 2 is input.
The phase is advanced by outputting the clock signal, and the signal CO is output from the 0 end to the OR gate 3.

The flip-flop 22 of the phase control circuit 2 inputs the inverted sign of the comparison output from the phase comparator 1 + 1co by the inverter 25 to the D terminal, and inputs the first stage output R of the N-stage read counter 14.
The second stage output Rφ2 after one clock of φ1 is manually input to the CK terminal, and the output is input to the D of the flip-flop 24.
Enter at the end. Then, by the 2-frequency divided clock MCK 2 inputted to the CK terminal of the flip-flop 24, only one clock of the 2-frequency divided clock MCK 2 is outputted, and a phase delayed signal 8R is outputted from the Q terminal to the OR gate 3.

The OR gate 3 inputs the phase advance signal CO and the phase delay signal BR output from the phase control circuit 2, and performs OR processing.
The frequency of the gate output is divided by two by a frequency divider 4, and the divided output is supplied to a selector 9 as a clock selection signal S. However, normally, the output of the OR gate 3 is zero and does not output anything and is uncontrolled.

On the other hand, the master clock generator 5 generates a master clock MSN with a frequency 2nf that is an integral multiple of 2n of the frequency f of the required read clock RcLx, which is supplied to the read counter 14 that generates the selection signal S of the selector 12 of the elastic memory January 0.
is generated and output to the 2-frequency divider 7 and the analogue 81.82.

The 2-frequency divider 7 inputs the master clock MSK output from the master clock generator 5 by inverting its sign using the inverter 6, divides the frequency into two, and outputs a positive output Q whose frequency is half that of the master clock MSK. An inverted output port of the phase difference π whose sign has been inverted is outputted to an AND gate 81 and an AND gate 82 .

81.82 gates the output Q and the inverted output port of the frequency divider by the master clock MSK output from the master clock generator 5, so that the frequency is 172 times the frequency of the master clock MSK. The selector 9 generates a clock CKO and a clock CKπ with a phase difference of π.
Output to.

The selector 9 inputs the clock CKO and the clock CKπ output from the analog game 1-81 and 82, and selects one of them using the selection signal S of the output of the frequency divider 4 which is the output of the phase control circuit 2. do. Usually, the repetition frequency is 172 of the frequency 2nf of the master clock MSK.
The divided-by-2 clock MCK 2 whose phase is advanced by adding one pulse of the master clock MSN is selected and outputted to the output gate 10.

Output game 0 is the 2-frequency divided clock MS of the output of the selector 9.
K2 is the phase delayed signal B of the output of the phase control circuit 2.
The flip-flop 21 of the phase control circuit 2 inputs the level "L" of the comparison output pco of the phase comparator 1, and the flip-flop 22 inputs the comparison output pco of the phase comparator 1. In the normal case where the level "■" which is the inversion of the level "L" of the output PCO is input, a divided-by-2 clock with an advanced phase is obtained by adding one pulse of the master clock MSK to the divided-by-2 output of the master clock MSK. MCK 2 is output to the n frequency divider 20, but the flip-flop 21 of the phase control circuit 2 inputs the level "H" of the comparison output PCO of the phase comparator 1, and the flip-flop 22 inputs the comparison output PCO of the phase comparator 1. In the case of an abnormality in which a level "L" which is an inversion of the level "H" of the PCO is input, the sign of the phase delay signal BR output from the phase control circuit 2 is different from that of the inverter 1.
One pulse of the master clock MSK is removed from the divided-by-2 clock MCK2, which is inverted by 1 and gated off by one clock at the output gate NO, and whose phase is advanced. Output to frequency divider 20.

As described above, the phase control circuit 2 of the simple integral type DPLL phase control method according to the present invention uses the output Rφ1. Since Rφ9 is directly used to control the phase comparison output pco, the circuit scale is reduced and simplified, and the problem is solved.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a simple integral type DPLL phase control system according to an embodiment of the present invention, and FIG. 3 is a time chart for explaining its operation.

The numbers ■■ etc. in the block diagram of FIG. 2 correspond to the numbers ■■ etc. in the time chart of FIG. 3.

In the block diagram of FIG. 2, a phase comparator l is composed of an SR flip-flop, and an N-stage read counter 1 generates a selection signal S for a selector 12 of an elastic memory 10.
4 and the first stage output Rφ1■ of the N-stage write counter 13 that creates the write address of the latch 11. The phase is compared at each rising edge of the first stage output Rφ1■ of the N-stage write counter 13, and the comparison output pco■ is sent from the 0 output terminal to the phase control circuit. Output to 2.

Flip-flop 2122.2324 of phase control circuit 2
is composed of D flip-flops, and flip-flop 2
1 inputs the comparison output pco■ from the phase comparator 1 as it is to the D terminal, and outputs the first stage output Rφ of the read output rank 14 of the N stage.
The final stage output Rφ8■ before the I clock of 1■ is input to the CM terminal and taken in, and the 0 output is sent to the flip-flop 23.
input to the D end. And flip-flop 23 CK
According to the 2-frequency divided clock MCI 2 inputted at the 0 end, one clock of the 2-frequency divided clock MCI 2 is outputted, the phase is advanced, and the signal CO2 is outputted from the 0 end to the OR gate 3.

The flip-flop 22 of the phase control circuit 2 inputs the inverted sign of the comparison output pco from the phase comparator 1 by the inverter 25 to its D terminal, and outputs the first stage output Rφ of the N-stage read counter 14.
The second stage output Rφ2■ after one clonk of 1■ is manually input to the CK terminal, and its Q output is input to the D terminal of the flip-flop 24. Then, by the 2-frequency divided clock MCK 2 inputted to the CK terminal of the flip-flop 24, only one clock of the 2-frequency divided clock MCK 2 is output, and the phase delayed signal Bl? ■Output B from the 0 end to the OR gate 3.

The OR gate 3 manually performs OR processing on the phase advance signal CO and the phase delay signal nR output from the phase control circuit 2.
The frequency of the gate output is divided by two by a frequency divider 4, and the divided output is supplied to a selector 9 as a clock selection signal S. However, normally, the output of the OR gate 3 is zero and does not output anything and is uncontrolled.

On the other hand, the master clock generator 5 generates a master clock MSK■ with a frequency 2nf, which is an integral multiple of 2n of the frequency f of the required read clock RCLll, to be supplied to the read counter 14 of the elastic memory. and is output to AND gates 81 and 82.

The 2 frequency divider 7 manually inverts the sign of the master clock MSK which is the output of the master clock generator 5 using the inverter 6, divides the frequency into 2, and generates a positive output 0 whose frequency is half that of the master clock MSK. The inverted output port of the phase difference π whose sign is inverted is outputted to the AND gate 81 and the AND gate 82 .

81.82 gates the output 0 and the inverted output 0 of the frequency divider by the master clock MSK which is the output of the master clock generator 5, so that the frequency is 172 of the frequency of the master clock MSN. A clock CKO■ and a clock CKπ■ having a phase difference of π are generated and output to the selector 9.

The selector 9 selects the clock C output from the AND gate 8L82.
KO■ and clock CKπ■ are inputted, and one of them is selected by the selection signal S [phase] of the output of the frequency divider 4 which is the output of the phase control circuit 2. Then, normally, the frequency nf whose repetition frequency is 1/2 of the frequency 2nf of the master clock MSK is selected and the divided-by-2 clock @MSK2 whose phase is advanced by adding one pulse of the master clock MSK is selected and output. Output to gate 10.

The output gate 10 outputs the output of the selector 9 divided by two clock 0.
M5K2 is subjected to AND processing using a sign-inverted signal from the inverter 11 of the phase delayed signal BR■B output from the phase control circuit 2. Then, as shown in (2), the flip-flop 21 of the phase control circuit 2 inputs the level "'L" of the comparison output PCO of the phase comparator 1, and the flip-flop 22 inputs the level "'L" of the comparison output PCO of the phase comparator 1. In the normal case, the inverted level ``■'' is input without control, and the phase-advanced divided-by-2 clock ■, which is the output of the master clock MSK divided by two and one pulse of the master clock MSK added, is input to n.
It is output to the frequency divider 20, but as shown in (2), the phase control circuit 2
The flip-flop 21 is the comparison node 1 of the phase comparator 1.
To import the level “H” of co, follow the steps to ■ (, MC
A phase advance control pulse with a width of K pulses is generated, and as shown in B, the flip-flop 22 outputs the comparison output P of the phase comparator 1.
When taking in the level "L" which is the inversion of the level "+1" of CO, generate a phase delay control pulse with the MCK pulse width as shown in (B) and delay the phase signal Bl? of the output of the phase control circuit 2. The sign of is inverted by the inverter 11 and the output
At 1/10, the gate is turned off by one clock, and one pulse of the master clock MSN is removed from the divided-by-2 clock ■ whose phase is advanced, and the divided-by-2 clock @ which is controlled with a phase delay is converted to an n frequency divider. Output to 20.

As described above, D of the simple integral formula of the embodiment of the present invention shown in FIG.
In the PLL phase control method, the phase control circuit 2 is
Output R of read counter 14 of elastic memory 10
Since φ1+1φ8 is directly used to control the phase comparison output pco, the circuit scale is reduced and simplified, and there is no problem of ζ.

〔Effect of the invention〕

As explained above, according to the present invention, the phase control circuit of the DPLI directly uses the output of the read counter of the elastic memory to control the comparison output of the phase comparator, so the circuit scale is reduced and simplified. In addition, it is possible to respond to changes in the number of stages of elastic memory or bit rate with a small change in circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the configuration of the simple integral type DPLL phase control system of the present invention, FIG. 2 is a professional diagram showing the configuration of the simple integral type DPLL phase control system of the embodiment of the present invention, The third leap is a time chart for explaining the operation of the embodiment of the present invention, and FIG. 4 is a block diagram of a conventional DPLL phase control system. In the figure,

Claims (1)

[Claims] A latch (11A
) to write N write data (W_D_A_T_A) and count another read clock (R_C_L_K).
Using the output of the read counter (14) of the stage as a selection signal, the read data (R_D_A
Elastic memory (10A) to read _T_A)
A phase comparator that compares the phases of the first stage output (Rφ1) of the N-stage read counter (14) of the elastic memory (10A) and the first stage output (Wφ1) of the N-stage write counter (13) at each rising edge. (1) Phase comparison output (PC
The selection signal s is the frequency-divided output of one output of the phase control circuit (2) which obtains the phase advance signal (CO) or the phase delay signal (BR) by integrating the signal O), and the elastic memory (
A positive output (Q) obtained by dividing the master clock (MSK) with a frequency (2nf) that is an integral multiple of the frequency (f) of the required read clock (R_C_L_K) of 10A) and a negative output (Q) whose phase is inverted. Select a divided-by-2 clock (MCK2) of two series (CKo, CKπ) whose repetition frequency obtained by processing by the master clock (MSK) is half that of the master clock (MSK) and whose phase difference is π. Clock (MCK2
) and the inverted signal of the phase delay signal (BR), and the gate output is divided by n to obtain the required read clock (
In the DPLL phase control method for obtaining R_C_L_K), a phase comparator that compares the phase of the first stage output (Rφ1) of the N-stage read counter (14) and the first stage output (Wφ1) of the N-stage write counter (13). (1) Output comparison output (PC
O) is the final stage output (Rφ_N) and second stage output (Rφ2) before and after the first stage output (Rφ1) of the read counter (14).
The outputs of the flip-flops (21, 22) are further divided into 1 by the selected 2-divided clock (MCK2).
Flip-flop that takes in only the clock (23, 24
), and normally the phase control circuit (2) is provided with a final stage output (
Rφ_N), the phase comparison output (PCO) level “L”
” and outputs the second stage output (R
φ2) takes in the level “H” of the inverted signal of the phase comparison output (PCO) and is not controlled, but the final stage output (Rφ
When the level “H” of the phase comparison output (PCO) is taken in by the second stage output (Rφ2), the phase delay control is performed on the DPLL, and the level of the inverted signal of the phase comparison output (PCO) is set “L” by the second stage output (Rφ2). A simple integral type DP characterized by controlling the phase of the DPLL when it is taken in.
LL phase control method.