JPS6369480A - Control circuit - Google Patents

Abstract

PURPOSE:To form a cycle detection circuit into a single unit and control a motor stably, by arranging a delay circuit and two hold circuits even when the control of a plurality of systems is executed. CONSTITUTION: From a cycle detection circuit 5, the output of the result of output data according to the input pulse of a speed control system and output data according to the input pulse of a rotary phase control system which are added to each other is directed as data signal to signal lines 51. The output is directed to a D/A converter 8 for input via a first hold circuit 6 and a second hold circuit 7 working with the output of a delay circuit 4. From the D/A converter 8, the output of voltage according to the data signal is directed to a signal line 80. From a driving circuit 9, specified current according to voltage applied to the signal line 80 is fed to a motor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a control circuit for controlling motor rotation using digital circuit technology.

BACKGROUND OF THE INVENTION Conventional motor control using digital circuits is based on a plurality of pulses of human power corresponding to the rotational speed of the motor.
The period detection circuit output to the A converter) is
The same number of circuits as the number of pulse input systems were required, which caused an increase in circuit scale (for example, National Technical Revo-To, Vol. 28, No. 3, June 1982 issue,
■Published by Matsucho Techno Research, P2S5, Fig. 19) Problems to be Solved by the Invention Therefore, in the above configuration, the same number of period detection circuits as the number of input pulse systems are required, which makes it difficult to achieve miniaturization. There was a problem. If you simply try to use part or all of the period detection circuit in common, 7
Since the timing of the processing output varies because one processing is completed before another processing is completed, the time from the input to the output of the period detection circuit fluctuates, making stable control of the motor impossible. Ta.

In view of the above-mentioned problems, the present invention realizes miniaturization of the circuit by sharing part or all of one period detection circuit for multiple pulse input systems, and also enables the D/A converter to By giving the output signal after a certain period of time from the application of the input pulse to the period detection circuit, stable response control of the motor is provided.

In order to solve the problem described in "Means for Solving the Problem," the control circuit of the present invention sequentially performs period detection processing on a plurality of input pulses,
A first hold circuit outputs and holds the first output immediately after processing is completed, a delay circuit delays the input pulse by a predetermined time and outputs it, and the output of the first hold circuit is inputted and outputs the delay circuit. A second hold circuit is provided that outputs and holds the input data from the first hold circuit when a pulse is applied, and the output of the second hold circuit is sent to the controlled object via a D/A converter. This is used as a control signal.

Effect The present invention has the above-described configuration, so that no matter what timing the inputs of the plurality of pulse systems are applied to,
By combining period detection processing for each input pulse and predetermined time delay output processing from each input pulse, the output signal of the period detection processing is transferred to the D/A after a predetermined time for each input system.
can be input to the converter. In other words, by sharing the period detection circuit, the circuit can be miniaturized, and fluctuations in response time of control signals can be eliminated, making stable motor control possible.

Embodiment Hereinafter, a control circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the control circuit of the present invention. In Figure 1, 1 is the motor, 2 is the speed control system (
A pulse generator (hereinafter abbreviated as FG) of a speed system (hereinafter abbreviated as FG) outputs pulses with a period proportional to the rotation period of the motor 1 to a signal line 20. Reference numeral 3 denotes a pulse generator (hereinafter abbreviated as PC) of a rotational phase control system (hereinafter abbreviated as phase system), which outputs a pulse signal of one pulse per one rotation of the motor 1 to a signal line 30. 4 is a delay circuit which outputs a control pulse signal to the signal line 40 after each predetermined time period from the application of the pulse signal to the signal line 20, 30. 5 is a period detection circuit, and line 13 is 20 or 30.
It operates by applying a pulse signal given to , and outputs a data signal corresponding to each period or phase to the signal line 51 and a control pulse signal to the signal line 52. Reference numeral 6 designates a first hold circuit which inputs the data signal on the signal line 51 by applying a control pulse signal to the signal line 52, and outputs and holds the data signal on the signal line 60 as a Y-ta signal. 7 is a second hold circuit which controls the signal line 6 by applying the control signal given to the signal line 40.
A data signal of 0 is input and is output and held as is to the signal line 70 as a data signal. A D/A converter 8 outputs a voltage corresponding to the data signal applied to the signal line 70 to the signal line 80. 9 is a drive circuit and a signal line 80
A predetermined current corresponding to the voltage applied to the motor is supplied to the motor.

The operation of the control circuit configured as above will be explained using FIG. 1. Signal line 20 or 30 as the motor rotates
The period detection circuit operates by applying a pulse signal given to the period detection circuit, but if one pulse signal is input while the other period is being detected, the input time is memorized and one period detection circuit is activated. After the process is completed and a data signal is output to the signal line 51 and a control pulse signal is output to the signal line 52, the other period detection process is started and a similar output is obtained. Further, in the delay circuit, if the delay time is appropriately set in consideration of the time required for each period detection process, the data signal is transmitted to the D/A converter after a certain period of time from the application of the pulse signal. Here, the operation of the period detection circuit in this embodiment is such that when an input pulse is applied to one system, it generates output data corresponding to the amount of change between the application time and the previous application time, and The result of adding the output data obtained in the same way in the system is outputted as a data signal to the signal line 51, and immediately after that, a control pulse signal is outputted to the signal line 52.

As described above, according to this embodiment, the motor l, PO2, PO2, period detection circuit 5, and first hold circuit 6
, the second hold circuit 7 operated by the output of the delay circuit 4, the D/A converter 8, and the drive circuit 9 constitute a speed system and phase system control loop to realize a stable motor response. Rotation control. Furthermore, since only one period detection circuit is required, the circuit scale can be reduced.

FIG. 2 shows another embodiment of the present invention, in which a circuit consisting of D-type flip-flops 601 to 604 is used as the first hold circuit 6. Similarly, a circuit consisting of D-type flip-flops 701 to 704 is used as the second hold circuit 7. Further, the delay circuit 4 uses monostable multivib breaks 401 to 404, resistors 405 to 408, capacitors 409 to 40C, and an OR circuit 40D. The other configurations are similar to the embodiment shown in FIG.

The operation of the control circuit configured as described above will be explained below with reference to FIGS. 2 and 3. Among the monostable multivibrators, monostable multivibrators 401 and 403 are triggered by the rising edge of the input signal, and monostable multivibrators 402 and 404 are triggered by the falling edge of the input signal. When the monostable multivibrator 401 detects the rise of the pulse signal on the signal line 20, the signal output to the signal line 421 becomes high level, and after a time corresponding to the time constant determined by the resistor 405 and capacitor 409 has elapsed, the signal is output to the signal line 421. line 42
The signal output to 1 becomes low level. Next, when the monostable multivibrator 402 detects the fall of the signal on the signal line 421, the signal output to the signal line 422 becomes high level, and after a period of time corresponding to the time constant determined by the resistor 406 and the capacitor 40A has elapsed. , signal line 42
The signal output to 2 becomes low level.

In other words, the time constant of the resistor 405 and capacitor 409 determines the pulse delay time, and the resistor 406 and capacitor 4
The pulse width is determined by the time constant of 0A.

Signal of signal line 424 and signal line 422 obtained in the same way
By inputting the signal to the OR circuit 40D, the re-input ORed signal is output to the signal line 40. Further, the D-type flip-flop used in the hold circuits 6 and 7 takes in data and holds the output only at the rising edge of a signal.

Furthermore, the output timing of the data signal on the signal line 51 and the control pulse signal on the signal line 52 output from the period detection circuit is as follows.
In this embodiment, the control pulse signal is set to rise after the data signal is first output and the D-type flip-flop used in the first hold circuit 6 can accurately capture the data signal. Except for the circuit 4, the first hold circuit 6, and the second hold circuit 7, the circuit configuration and operation are the same as in the embodiment shown in FIG. Then the third
The figure shows the timing of this embodiment, in which the speed-based pulse signal a is a signal appearing on the signal line 20 of FIG. 2, the phase-based pulse signal a is a signal appearing on the signal line 30 of FIG.
Control pulse signals C and e are the signals appearing on signal lines 502 and 40, respectively, in FIG. 2, and data signals d and C are signals appearing on signal lines 60 and 70, respectively, in FIG. 2. Figure 3 shows the timing when two systems of input pulses are input almost simultaneously. First, when the speed system pulse signal a is applied, the speed system period detection process starts, but that process is completed. If the phase-based pulse signal is input manually before the speed-related period detection process is completed, the phase-based period detection starts immediately. The output data signal is
Upon completion of each cycle detection process, the data signal d is output to the first hold circuit, and is taken into the first hold circuit by the rise of the control pulse signal C that is output immediately thereafter, and the data signal d is updated. Next, the data signal d is taken into the second hold circuit and the data signal f is updated by the rise of the control pulse signal e which is output after a certain period of time T3 and T4 from the input pulse No. 14 in the delay circuit. That is, the speed system period detection process is performed during the period T1, and the phase system period detection process is performed during the period T2.

As described above, according to this embodiment, by providing the delay circuit 4 and the hold circuits 6 and 7 as shown in FIG.
After a certain period of time for the two pulse signal inputs, D/
This is effective in transmitting data signals to the A converter, configuring a stable speed system and phase system control loop for the motor, and reducing the circuit scale by unifying the period detection circuit.

FIG. 4 is a block diagram showing an example of the arrangement of the period detection circuit in the first and second embodiments. 501 is a clock generation circuit which outputs a clock for operating the counter. A counter circuit 502 continues to count in synchronization with the output clock of the clock generation circuit 501 and outputs its digital value. 503 is a micro comb bib,
- counter circuit 502 by interrupt program.
inputs the output of the input pulse, calculates the period of the input pulse, and outputs a signal according to the period to the terminals 514+ 515+ 516+ 5
17, the control signal is output to the output terminal 513. 504
is an interrupt circuit which is operated by one pulse applied to the input terminals 51) and 512, and determines the interrupt block diagram (8%) and outputs it to the microcomputer 503.

505 is RAM (random access memory),
The memory 7506 that can be read and written is a ROM (read-on memory), which is a read-only memory that stores 7 interrupt programs. Explain the operation. First, when a pulse signal is applied to the input terminal 51) or 512, an interrupt program signal determined by the interrupt circuit 504 is input to the interrupt terminal of the microcomputer 503. The microcomputer executes the interrupt program by inputting the interrupt signal. First, the output data of the counter circuit 502 is input and stored in the RAM 505, the amount of change from the counter data input at the previous interrupt is calculated, and output data is obtained according to the amount of change.

In the same way, data for output of another system is obtained. When output data is obtained through each process, it is added to the other output data and output to output terminals 514, 515.5.
16.517, and immediately thereafter outputs a control pulse signal to the output terminal 513.

In addition, 1. In the second embodiment, the number of motors is limited to one, but the same effect can be obtained even if the number of motors to be controlled is increased and the number of input pulses and output systems is increased.

Further, in the first and second embodiments, four signal lines for the data signal were used to form a 4-bit signal, but the same effect can be obtained with any number of bits of the signal.

Effects of the Invention As described above, according to the present invention, even when controlling multiple systems, by providing a delay circuit and two hold circuits, a single cycle detection circuit can be used, which reduces the circuit scale and provides stable motor control. It becomes possible to do this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a control circuit in a first embodiment of the present invention, FIG. 2 is a block diagram including a specific circuit of the control circuit in a second embodiment, and FIG. This figure shows the relationship between the signals in FIG. 2 and is also a timing diagram, and FIG. 4 is a block diagram of the period detection circuit in the first and second embodiments. 1...Motor, 2,3...Pulse generator, 4...Delay circuit, 5...Period detection circuit, 6... First hold circuit, 7...
...Second hold circuit, 8...Digital-
Analog converter, 9... Drive circuit. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 3 Figure 4

Claims (2)

[Claims] (1) A motor, a plurality of pulse generators that obtain pulse signals with a period corresponding to the rotation speed of the motor, a predetermined data signal corresponding to the output pulse signal period of the plurality of pulse generators, and a first control. a period detection circuit that outputs a pulse signal; a first hold circuit that captures the data signal by applying the first control pulse signal and holds the output;
a delay circuit that outputs a second control pulse signal delayed by a predetermined time from application of the output pulse signals of the plurality of pulse generators; and an output signal of the first hold circuit for application of the second control pulse signal. a second hold circuit that captures and holds the output signal, a digital-analog converter that converts the output signal of the second hold circuit into a voltage corresponding to the output signal, and a digital-analog converter that converts the output signal of the second hold circuit into a voltage corresponding to the output voltage of the digital-analog converter; A control circuit comprising: a drive circuit that provides a drive current. (2) The period detection circuit includes a clock generation circuit, a counter circuit that counts the clocks generated by the clock generation circuit, and a change in the counter circuit from the time of the previous pulse input upon receiving a pulse signal from the pulse generator. The control according to claim (1), characterized in that the control includes a processing circuit that detects a quantity, outputs a digital value of the value, and outputs a control pulse signal immediately after outputting the digital value. circuit.