SU1534724A1 - Digital speed governor - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control DC motors. The purpose of the invention is to improve the accuracy of regulation. The device contains an input driver 1, a synchronizing generator 2, a control block 3, the output of which is connected to the buffer register 12 and the trigger 15. The inputs of the adder 13 are connected to the outputs of the register 12 and the counter 9. The output of the adder 13 is connected to the input of the counter 11. The digital speed controller has the combined law of regulation is proportional and astatic. The value of a given statism is chosen from the analysis of permissible dynamic characteristics. 2 Il.

Description

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The invention relates to electrical engineering and can be used in industrial and commercial electric drives.

The purpose of the invention is to improve the accuracy of regulation.

FIG. 1 shows a digital speed controller; in fig. 2 - time diagram of the regulator.

The digital speed controller contains the input driver synchronization generator 2 control unit 3, first 4, second 5, third 6 and fourth 7 elements OR, first 8S second 9, third 10 and fourth 11 counters, buffer register 12, adder 13, first 14 , second 15, third 16 and fourth 17 triggers and delay element 18. The output of the input shaper 1 is connected to the first input of the control unit 3, the first element OR 4 and the subtractive counting input of the second counter 9. The output of the synchronous generator 2 is connected to the first element OR 4 and the second input of the control unit 3, the first output of which is connected to the second input C 1 5 and the third 16 flip-flops and the write enable input of the buffer register 12, the second output with the write enable input of the third counter 10 and the input R of the first trigger 14, the third output with the second input of the input driver 1. The output of the first element OR 4 is connected: about the counter inputs of the first counter 8 and the third counter 10, the higher bits of which are connected to the second element OR 5, m younger ones - with m inputs of the buffer register 12, and the transfer output - with input C of the first trigger 14. First output the first counter 8 is connected to the summing counting input of the second counter 9, the second output is connected to the input of the fourth element OR 7, the third output with the counting input of the fourth counter 11 and through the delay element 18 to the input S of the fourth trigger 17. The output of the second element OR 5 is connected to the input second trig Hera 15, the output of which is connected to the input of the third element SHI 6, the output of which is connected to the input of the fourth element OR 7 and the input Reset of the second counter 9, whose outputs m are connected to the m inputs sum of the torus 13, the other m inputs of which are connected cm outputs of the buffer register 12,

-

 ,

ten

15

20

25

thirty

35

40

45

50

55

am outputs with m inputs of the fourth counter 11, the counting input of which is connected to the output of the fourth element OR, and the transfer output - to the input C of the fourth trigger 17. Input D of the first trigger 14 is connected to the common power bus, and the output to the input D of the third trigger 16 the output of which is connected to the input of the third element OR 6 and the input R of the fourth trigger 17, the D input of which is connected to the common bus, and the output through the power amplifier 19 is connected to the control object 20.

The regulator works as follows.

The input driver 1 receives a signal from the speed sensor of the control object 20, in particular, it may be an alternating voltage from the output of the alternator (Fig. 2a), mounted on the shaft of a direct current motor, the speed of rotation of which is controlled by the proposed regulator. This is possible because the frequency of the alternating voltage of the generator is uniquely related to the speed of rotation of the engine. The input driver 1 generates rectangular pulses (Fig. 26) with the period of the input signal and the duration determined by the pulse from the third output of the control unit 3 (Fig. 2e). According to them, the control unit 3 generates three control pulses. The pulses from the output of the input shaper 1 block the operation of the first 8 and third 10 counters. In the absence of the contents of the third counter 10 is decremented with the frequency of the clock generator

2 (FIG. 2c), and the first counter is 8

melts in the frequency divider mode. Cycle

measuring the duration of the period of the input signal begins with recording to the third counter 10 by pulse (Fig. 2e) from the second output of the control unit 3 the number K, the code of which is set on the n + m parallel inputs of the counter 10

to t „/ gay-iyi / ts,

where G is the nominal value of the adjustable frequency period; U G is the permissible deviation of the regulated period from the nominal (ala or regulation statism; Gs is the period of the synchronous generator.

Since the contents of counter 10 are decremented between pulses following from the output of input driver 1, the follow-up period is equal to the period of the input signal, then at the time of rewriting in the second counter 9 there is the number where Kig, m

 and l the current measured value of the adjustable period. YU

Within the limits of a given statism of regulation, the number M can take on the value 06M 2iP / Tc.

Thus, the number M determines the deviation of the adjustable period from the nominal value.

15

In the event that TI} M is large and out of the given statism, i.e. a pulse appears at the transfer output of counter 10, setting the first trigger 14 to unity. This trigger is triggered by a pulse from the second output of control unit 3 (Fig. 2e).

If the value is small, i.e. MS 52AT / TC, then at the output of the second element OR 5, at the time of the appearance of a pulse (Fig. 2d) at the first output of control unit 3 is a unit that is rewritten into the second trigger 15, as well as the contents of the first trigger 14 into the third trigger 16 along pulse (Fig. 2d) from the first output of control unit 3.

Thus, the unit at the output of the third element OR 6 testifies to the exit of Ti, m from the given statism.

The pulse number M (Fig. 2d) is written into the buffer register 12, and if Tism is within the limits of statism, the number M is added to the contents of the second counter 9 on the adder 13. The results are complicated — the number L is written in four - the th counter 11 pulse from the third output of the first counter 8, operating in the mode of the frequency divider. The frequency F.y of the following pulse determines the switching frequency of the power amplifier 19 and is selected by the designer at the design stage. Moreover, where P is an integer, a FC 1 / Gs.

The fourth counter I1 decrementiru-. pulses from the second output of the first counter 8 with a frequency F, and 2 AI

F k

g

five

0

five

0

Counter 11 is decremented only if it is within the prescribed statism of regulation and at the output of the third element OR 6 is zero.

In this case, the pulse at the output of the transfer of the fourth counter 11 is through the time C L / F.

At the beginning of each period of the frequency Fa, the fourth trigger 17, via delay element 18, is set to input S to one and after time is reset to zero to input C with a pulse coming from the transfer output of counter 11. Thus, at the output of the fourth trigger 17, a sequence of width-modulated control pulses is formed with a duration determined by the deviation of the adjustable period from the nominal value and the frequency specified at the design stage. These pulses are fed through power amplifier 19 to control object 20.

If the value of Ti% m is large and, the fourth trigger 17 is reset to .nol on input R.

If value

TC5M is small and M

2 & T

five

0

g

0

five

then the trigger 17 is set to one at input S, and since the counter 1I is blocked until the end of the adjustable period at the clock input, it is not reset at input C to zero, thereby providing a change in the fill factor from zero to one. The above described refers to a proportional speed control channel.

The summing counting input of the second counter 9 receives pulses from the first output of the first counter 8, the frequency of which is equal to the nominal value of the adjustable frequency: FH 1 / H, the subtracting counting input of the second counter 9 receives pulses with a frequency of FM} M 1 / Gi% m If T ", m is within the specified statism, then the counter 9 is not blocked by the Reset input, and the contents of this counter increase with and decrease with nP44eM M ° being a negative number, i.e. senior bit is one, and positive - high bit is zero. In case of equality, the contents of the counter

9 does not change. Thus, a digital speed controller with a comparison organ in the form of a reversible counter has an astatic characteristic.

The contents of the counter 9 corrects the C number M so that the L number in the established mode provides such a Filling factor of the pulses up to J Pressure, at which the PM9M value is equal to the nominal value.

 The digital speed controller has a combined law of regulation, iropordional and astatic, thereby guaranteeing high dynamic and accuracy characteristics. This controller has only a digital information processing path, which significantly improves the control accuracy over a wide temperature range, simplifies the controller and increases its reliability. The value of a given statistic is chosen from the analysis of admissible dynamic characteristics and a proper 2 margin for stability of the entire control system, thereby significantly expanding the scope of application of the regulator.

Claims (1)

3 claims A digital speed controller containing an input driver, a synchronous generator, the first and second counters, and a key power amplifier, which is different - H, in order to increase the control accuracy, a control unit, four elements OR, the third and fourth counters, a buffer register, an adder, four flip-flops and a delay element, the output of the input shaper is connected to the first input of the control unit, the first OR element and the subtracting counting input of the second counter, the output of the clock generator is connected to the first the second OR element and the second input of the control unit, the first output of which is connected to the input C of the second and third flip-flops and the write enable input of the buffer register, the second output to the write enable input of the third counter and the input R of the first trigger, the third output , the output of the first element OR is connected to the counting input of the first and third counters, n high bits of which are connected to the second element OR, m younger ones - to m inputs of the buffer register, and transfer output - to input C of the first tr the first output of the first counter is connected to the summing counting input of the second counter, the second output - with the input of the fourth OR element, the third output - with the counting input of the fourth counter, and through the delay element - with the S input of the fourth trigger, the output of the second OR element is connected to the input D of the second trigger, the output of which is connected to the input of the third element OR, the output of which is connected to the input of the fourth element OR and the input Reset of the second counter, m outputs of which are connected to m inputs of the adder, the other m inputs to Connected to the GA outputs of the buffer register, am outputs to the m inputs of the fourth counter, the counting input of which is connected to the output of the fourth OR element, and the transfer output to the input C of the fourth trigger, input D of the first trigger is connected to the common bus, and the output to D of the third flip-flop, the output of which is connected to the input of the third element OR and the input R of the fourth trsger; D is the input of which is connected to the common bus and the output through the power amplifier is connected to the control object, the output of the rotational speed sensor is intended for Connecting to the first input of the input shaper. b 6 gde Hrf I I I I I II L Shch2