SU1524027A1 - Digital frequency regulator - Google Patents

Abstract

The invention relates to automation and can be used to control the frequency of rotation of electric machines. The purpose of the invention is to improve the accuracy of the controller. The regulator has an astatic regulation characteristic, and the measurement and conversion path of the adjustable parameter is purely digital, which does not introduce additional error. The controller contains a pulse shaper 1, a master oscillator 2, a pulse distribution unit 3, counters 4, 5, delay elements 6, 7, trigger 8, power amplifier 10. 2 Il.

Description

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ABOUT

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The invention relates to automation and can be used in systems for regulating the frequency of rotation of electric machines, as well as in other systems of automatic regulation.

The purpose of the invention is to increase the accuracy of the controller.

FIG. is presented (functional diagram of the regulator; figure 2 is a timing diagram explaining its operation.

The digital frequency controller contains a pulse shaper 1, a master oscillator 2, a pulse distribution unit 3, second and first counters 4 and 5, first and second delay elements 6 and 7, trigger 8, zero potential bus 9, power amplifier 10 , control object 1I, frequency divider 12, trigger 13, single-oscillators 14, shift register 15.

The regulator works as follows.

The input driver 1 generates square pulses with a period of adjustable frequency. These pulses, as well as the pulses from the generator 2 (Fig. 2a), go to block 3, which forms the following sequences of control pulses.

On the first (Fig. 2b) in the run of block 3, the pulses follow with the frequency of the FUJHM torus equal to F, / N, where F is the frequency of the generator 2; N is a positive integer.

The duration of the pulses at these outputs, as well as the shift between them, is equal to

smnh dt smm

The frequency F determines the switching frequency of, for example, key power amplifier 10, and accordingly, the magnitude of its dynamic loss.

At the third output (Fig. 2d) of block 3, the pulses follow with a frequency F, a multiple of frequency F. The frequency F is determined by the quantization step size of the output signal output to the (key) power amplifier 10.

At the fourth output of block 3, pulses of duration less than T (,, follow with a frequency equal to the current value of the adjustable frequency.

At the fifth output of block 3, the pulses follow with a frequency equal to the nominal value of the controlled frequency with a duration shorter than cwH «/ 2. The frequency F c (,, is obtained by dividing F (, by an integer K (fig. 2b).

The impulses on the fourth and fifth outputs of block 3 are triggered by the front and, accordingly, by the decay of the generator 2 pulses, which is necessary for the trouble-free operation of gchegchik 4, which receives nMnyjibcbi from the fourth output of block 3 at a frequency Fn

FL out

. If F P5J-o the contents of counter 4 is increased, and if F p, r i, then decreases, and the rate of change of the contents is determined by the value of AF F in the case of equality Fp F j, the contents of counter 4 does not change.

By pulses from the first output of block 3 with a frequency FIJ, the contents of counter 4 are copied to counter 5, the contents of which are decremented with a frequency F by pulses from the third output of block 3.

The trigger 8 is set to one at the installation input (S) by a pulse from the second output of block 3 and reset to 0 by a pulse reset from the sact-ia output of counter 5 through time T equal to T Q 1 / F, where Q is the number in counter 4 at the time of recording its contents in the counter 5.

Thus, at the output of the trigger 8, a sequence of width-modulated pulses is formed with a given frequency of 7 and a duration defined by the value of Q. For Q O and Q M, the fill factor is zero and one, respectively. If the equality F ptr from the contents of the first counter 4 is fulfilled such that the fill factor has the value necessary to maintain a given speed.

Thus, a CYL rate controller with a measuring body in the form of a reversing counter has an astatic characteristic.

In the event that the Q number exceeds the digit of counter 4, then the maximum number determined by the digit of this counter is recorded from the transfer output through delay element 6. If the number Q is reduced to zero, then, according to the signal from the exit of the loan through delay element 7, the counter 4 is recorded O. Thus, the false operation of the controller associated with the overflow of the counter A is eliminated

The digital frequency controller allows to ensure the accuracy of the regulation, which is determined only by the accuracy of the master oscillator, since the entire measurement and conversion path of the controlled parameter is purely digital and does not introduce additional error.

Claims (1)

Invention Formula A digital frequency regulator containing a master oscillator, a power amplifier whose output is connected to the controller output, whose input is connected to the pulse driver input, as well as the first delay element and the first counter, the output of which is connected to the trigger reset input, differing By the fact that, in order to increase the accuracy of the controller, a pulse distribution unit has been entered into it, the second counter and a second delay element, the outputs of the master oscillator and pulse generator are connected respectively to the clock and information inputs of the pulse distribution unit, the first output of which is connected to the recording resolution input of the first counter, the counting input for whose subtraction is connected to the third output of the pulse distribution unit, the second input of which is connected to the setup input of the trigger connected by the output to the input of the power amplifier, information) the 5th input of the first counter is connected to the information output Meters withstand, and whose outputs transfer the loan are respectively connected via first and second elementy.zaderzhki, corresponding to 20 stvennoj write enable input and reset input of the second counter, the count input for the summation and subtraction counting input of which are respectively connected to the fourth 25 and the fifth outputs of the pulse distribution unit, the information input of the trigger is connected to the zero potential bus.