JPH01107688A - Servo device - Google Patents

Abstract

PURPOSE:To simplify a data distributing mechanism for changing over rotational speed by transmitting a result, in which an output data from a memory means transmitting a reference value data over a phase error detection means is multiplied by a decimal smaller than 1, over a speed detection means. CONSTITUTION:A preset data is sent to a cylinder phase system counter 11 measuring phase difference between a rotational phase signal and a reference phase signal for a cylinder motor 1 from a common memory 38. On the other hand, the data of the common memory 38 is transmitted over a cylinder speed system counter 12 measuring the cycle periods of the rotational speed signals of the cylinder motor 1 and a capstan motor 23 and a capstan speed system counter 28 through an adder 39 and decimal multipliers 40, 41. The dicimal multipliers 40 and 41 respectively multiply an output data from the adder 39 by a decimal smaller than 1 and output it.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a servo device for a rotating body equipped with phase error detection means and speed error detection means.

BACKGROUND OF THE INVENTION FIG. 4 shows a typical 4tlF' block diagram during playback of a servo system of a home video tape recorder. In FIG. 4, reference numeral 1 denotes a cylinder motor that drives a rotating cylinder to which a head for recording and reproducing video signals is attached, and a frequency generator 2 that generates an alternating current signal with a frequency that depends on the rotational speed of the rotating cylinder. and a position detector 3 that generates a position detection signal once per rotation. The frequency generator 2
The output signal is amplified and waveform-shaped by the FC signal amplifier 4, and the output is sent to the frequency divider 5 and the controller 6.
The output of the position detector 3 is amplified and waveform-shaped by a PG signal amplifier 7, and the output is supplied as a cent signal to the frequency divider 5 and a 1/2 frequency divider 8. Further, the output signal of the clock generator 9 is passed through a frequency divider 10 to a cylinder phase system counter 11. Cylinder speed counter 12. Capstan phase system counter 32. Each of these signals is supplied to the capstan speed counter 28 as a clock signal.

The number of bits of the cylinder phase system counter 11 is 16 bits, and the 16 bit cylinder phase system RO
Precent data is supplied from M (memory exclusively for m extraction) 13, and its output is supplied to a decoder 14 and a latch 15 with 10 pins, and the first output of the decoder 14 is sent to the cylinder phase system counter 11 as a preset signal.
The second output is supplied to the delay circuit 16,
The output data of the latch 15 is supplied to a 10-bit DA converter (digital-to-analog converter) 17. Note that the latch 15 stores the LSB (
The lower 10 bits of data including the least significant bit are supplied.

Further, the output of the frequency divider 8 is supplied to the latch 15 as a load signal, the first output of the controller 6 is supplied as a load signal to the 8-bit lunch 18, and the second output is supplied as a preset signal. It is supplied to the cylinder speed system counter 12.

The cylinder speed system counter 12 has a 12-bit, 7-bit configuration, and precent data is supplied from a 12-bit cylinder speed system ROM 19, and the lower 8 bits including the LSB of the output data are sent to the launch 18. The output data of the latch 18 is an 8-bit D
−A converter 20.

Further, the outputs of the D-A converter 17 and the D-A converter 20 are combined by a combining circuit 21, and the output signal of the combining circuit 21 is sent to the cylinder motor drive circuit 22.
is supplied to.

On the other hand, a frequency generator 24 is connected to a capstan motor 23 for running the magnetic tape, and the output signal of the frequency generator 24 is amplified and waveform-shaped by an FC signal amplifier 25 and then supplied to a controller 26. The first output of the controller 26 is supplied as a load signal to an 8-bit latch 27, and the second output is supplied as a precent signal to a 10-bit capstan speed counter 28.

In addition, the output signal of the control head 29 which is recorded at regular intervals on the magnetic tape and played back is amplified and waveform-shaped by a control signal amplifier 30, and then supplied to a 10-bit latch 31 as a load signal. .

Clock signals are supplied from the frequency divider 10 to the capstan speed counter 28 and the 15-pin capstan phase counter 32, respectively. The capstan phase system counter 32 is supplied with a precent signal from the delay circuit 16, and among its output data, the LS
The lower 10 bits of data including B are supplied to the latch 31, and the output data of the latch 31 is the 10 bits of D.
-A converter 33. The capstan speed system counter 28 is supplied with preset data from a 10-bit capstan speed system ROM 34, and of the output data, the lower 8 bits including the LSB are supplied to the latch 27, and the output data of the latch 27 is is supplied to an 8-bit DA converter 35.

Further, the outputs of the D-A converter 33 and the D-A converter 35 are combined by a combining circuit 3G, and an output signal of the combining circuit 36 is supplied to a capstan motor drive circuit 37.

In FIG. 4, it is assumed that a frequency generator 2 connected to a cylinder motor 1 generates an AC signal of 6 cycles per rotation, and a frequency divider 5 performs a frequency division operation of 1/3,
It is assumed that the frequency divider 8 performs a frequency division operation of 1/2. In addition, according to the NTSC specifications (a standard for television broadcasting adopted in Japan and the United States), the reference rotation speed of the cylinder motor 1 is 1800 rpm, and at this time, the output frequency of the frequency generator 2 is 180 Hz, and the position detection The output frequency of device 3 is 30 llz. Therefore, a square wave having a phase dependent on the rotational phase of the cylinder motor 1 and a duty of 50% is obtained from the frequency divider 8, and this signal becomes the rotational phase signal. Also,
A clock signal of a constant frequency is supplied to the cylinder phase system counter 11, and when a predetermined count value is reached, the decoder 14 generates an output pulse.
The first output of 4 becomes the reference phase signal of the cylinder phase system, and the second output is the delay circuit 1 for tracking adjustment.
6 and becomes the reference phase signal of the capstan phase system. Furthermore, since a control reproduction signal depending on the running phase of the magnetic tape is obtained from the control head 29,
The output signal of the control signal amplifier 30 becomes a running phase signal of the capstan phase system.

On the other hand, the FC signal amplifier 4 obtains a rotational speed signal of the rotating cylinder, and the FC signal amplifier 25 obtains a rotational speed signal of the capstan.

At the leading edge of the output signal of the FC signal amplifier 4, the controller 6 first generates a load signal for loading the count value of the cylinder speed system counter 12 into the latch 18, and then generates a precent signal for the cylinder speed system counter 12. do. The capstan speed system controller 26 also performs the same operation as the controller 6. Therefore, the cylinder phase system latch 15 holds the measurement result of the phase difference between the cylinder rotational phase signal and the reference phase signal, and the cylinder speed The latch 18 of the system holds the measurement result of the period of the rotational speed signal, similarly, the latch 31 of the capstan phase system holds the measurement result of the rotational phase difference of the capstan, and the latch 2 of the capstan speed system holds the measurement result of the rotational phase difference of the capstan.
7 holds the measurement result of the period of the rotational speed signal of the capstan.

The output of the latch 15 (measurement output of the cylinder phase system counter 11) is converted into a DC voltage by the DA converter 17,
2 measurement output) is converted into a DC voltage by a D-A converter 20, and these DC voltages are combined by a synthesis circuit 21 to create a cylinder rotation error output signal.
The cylinder motor 1 is driven via the cylinder motor 2.

Further, the output of the latch 31 (measured output of the kissepsun phase system counter 32) is converted into a DC voltage by the DA converter 33, and the output of the latch 27 (measured output of the capstan speed system counter 28) is converted to a DC voltage by the DA converter 33.
5, these DC voltages are combined by a combining circuit 36 to create a capstan rotation error output signal, and the error output signal drives the capstan motor 23 via a capstan motor drive circuit 37. Driven.

Problems to be Solved by the Invention By the way, in FIG. 4, the cylinder phase system counter 11
．． Preset data is supplied to the cylinder speed system counter 12 and the capstan speed system counter 28 from separate ROMs, but these preset data are mainly prepared for double speed playback. For example, V
In the H3 NTSC specification, the relative speed between the rotating head and the magnetic tape during recording or normal (+1x speed) playback is approximately 5.13 m/sec, but when the magnetic tape is run at +9x speed in the 2-hour mode ( The output signal of the FG signal amplifier 25 is reduced to 1/9 by the controller 26.
If the frequency is divided into , the capstan motor 23 rotates at nine times the rotation speed, and therefore the running speed of the magnetic tape becomes nine times. ), since the scanning direction of the rotating head on the magnetic tape is equal to the normal running direction of the magnetic tape, the relative speed between the rotating head and the magnetic tape is slow, and the frequency of the reproduced horizontal synchronizing signal is approximately 4.8%. On the other hand, when a magnetic tape is run at 19x speed, the frequency of the reproduced horizontal synchronous signal No. 13 increases by about 5.4 percent. If the frequency of the horizontal synchronization signal changes significantly, the television receiver will be unable to follow it and the synchronization will be disrupted, so it is necessary to correct the relative speed so that it does not change. To explain this using +9x speed as an example, in order to correct the relative speed, it is sufficient to prepare preset data such that the count frequency of the cylinder phase system counter 11 is 4.8% higher than during normal playback. Preset data supplied to the cylinder speed system counter 12 and the capstan speed system counter 28 are also respectively set so that the speed error output becomes zero during synchronous rotation.

In this way, the cylinder phase system ROM13. Cylinder speed system ROM19. The capstan speed system ROM 34 has a number of data prepared in accordance with the type of double speed mode required. In the NTSC specification, the recording and playback time mode is
There are three types of modes: 2 hour mode, 4 hour mode, and 6 hour mode, so the number of data (number of addresses) required for each ROM
becomes quite large. For example, in each time mode, ±15 times speed, ±9 times speed, ±5 times speed, ±3 times speed.

If ±2x speed, ±1x speed, and 0x speed (stop) are required, different preset data must be prepared for all except +1x speed, and the number of addresses for each ROM is 37, and the When converting a system like the one shown in Figure 4 into an LSI (Large Scale Integrated Circuit), not only does the area of the ROM portion on the chip and the area of the address decoder portion attached to it become quite large;
There is also a problem in that it takes a lot of time to inspect the ROM data.

As a specific method for solving such problems, the applicant previously proposed in patent application No. 191020 of 1981 that an arbitrary bit can be extracted from a memory storing preset data for a cylinder phase system counter. proposed a device that distributes the high-order bit data of a number to a cylinder speed counter and a capstan speed counter, but since this method uses data from the memory as is, the cylinder speed counter and capstan speed counter For speed-related counters, a controller is required to match the data supplied from the memory with the actual operating conditions (FC frequency, clock frequency of each counter, etc.), and each time these operating conditions are changed, It was necessary to change the configuration of the controller.

Means for Solving the Problems In order to solve the above-mentioned problems, the servo device of the present invention includes memory means for supplying a plurality of reference value data for switching the rotational speed of the rotating body to the phase error detection means. , decimal multiplication means for multiplying the output data of the memory means by a decimal number smaller than 1 and supplying the result to the speed detection means.

According to the present invention, the above-described configuration makes it possible to simplify the data distribution mechanism for switching the rotational speed of the rotating body more than ever before, and furthermore, it is possible to construct a system that can flexibly respond to changes in specifications. .

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a servo device according to an embodiment of the present invention, and the same blocks as in FIG. 4 are designated by the same figure numbers. In the system shown in FIG. 1, preset data is supplied from the common memory 38 to the cylinder phase system counter 11 that measures the phase difference between the rotational phase signal of the cylinder motor 1 and the reference phase signal. Data from the common memory 38 is supplied via an adder 39 and a decimal multiplier 40 to a cylinder speed counter 12 that measures the repetition period of the rotational speed signal. Furthermore, the capstan speed counter 28 is supplied with data from the common memory 38 via the adder 39 and decimal multiplier 41.

The decimal multiplier 40 and the decimal multiplier 41 multiply the output data of the adder 39 by a decimal number smaller than 1 and supply the result to the cylinder speed system counter 12 and the capstan speed system counter 28, respectively. A specific example of the configuration is shown in FIG. In FIG. 2, the arithmetic logic clearing unit 50 is used as an adder;
The register 51 is supplied with 16-bit multiplicand data from the adder 39 in FIG.
Bit multiplier data is provided. shift register 52
16 right shift pulses are applied to the register 51.
is configured to transmit data to the arithmetic and logic unit 50 only when a shift carry from the shift register 52 occurs, and transmits zero at other times;
The arithmetic and logic operation unit 50 is configured so that addition command pulses are applied 16 times.

Now, the multiplicand data supplied to the register 51 is hexadecimal (4E20), that is, 20000 in lO base, and the multiplicand data supplied to the shift register 52 is 1.
Assuming that it is (8000) in hex and 32768 in decimal, when a 16-cycle pulse signal is supplied as the multiplication control signal, the data Rn of the shift register 52,
The shift carry Cn, the output data Dn of the arithmetic and logic unit 50, and the output data Sn of the right shifter 53 transition as follows.

n Rn Cn Dn
Sn ■ (4000) (0) (0000) (0
000)■(2000)(0)(0000)(0000
)■(1000)(0)(0000)(0000)■(
0800)(0)(0000)(0000)■(040
0)(0)(0000)(0000)■(0200)(
0)(0000)(0000)■(0100)(0)(
0000)(0000)■(0080)(0)(000
0)(0000)■(0040)(0)(0000)(
0000) [phase] (0020) (0) (00001 (0
000)■(0010)(0)(0000)(0000
)◎(000B)(0)(0000)(0000)@(
0004)(0)(0000)(0000)■(000
2) (0) (0000) (0000) [phase] (0001
)(0)(0000)(0000)[phase](0000
) (1) (4E20) (0000) The multiplication result is equal to the multiplicand (4B20) multiplied by the decimal 1.0.

Similarly, the multiplicand data supplied to the register 51 is hexadecimal (4E20), and the multiplier data supplied to the shift register 52 is hexadecimal (5555), 1
Assuming that it is 21845 in decimal notation, when a 16-cycle pulse signal is supplied as a multiplication control signal, data Rn of shift register 52, shift carry Cn, output data Dn of arithmetic logic unit 50, right shifter 5
The output data Sn of No. 3 transitions as follows.

n Rn Cn Dn Sn
■(2AAA)(1)(4E20)(0000)■(1
555)(0)(2710)(2710)■(OAAA
)(1)(61A8)(138B)■(0555)(0
)(30D4)(30D4)■(02AA)(1)(6
68A) (186A) ■ (0155) (0) (3345
)(3345)■(OOAA)(1)(67C2)(1
9A2)■ (0055) (0) (33E1)
(33E1)■ (002A) (1) (6
810) (19FO) [phase] (0015) (0
) (3408) (3408)■ (OOOA)
(1) (6824) (IAO4]O(00
02) (1) (6829) (IAO9) [
phase] (0001) (0) (3414) (3
414) [Phase] (0000) (1) (682A
) CIAOA) [phase] (0000) ('O)
(3415) (3415) The multiplication result in this case is 13333 in decimal, which is (4B20) of the multiplicand.
0.61 as a decimal. That is, (20000/3276
7) is also equal to ゛.

Therefore, the multiplicand data of the decimal multiplier shown in FIG. 2 is supplied from the common memo 1J38 via the adder 39 shown in FIG. 12 or the capstan speed system counter 28, the output data of the adder 39 can be multiplied by a decimal number smaller than 1.

Now, an outline of the operation when the VTR is in the playback state in the system shown in Fig. 1 will be explained.For convenience of explanation, specific numerical values will be used. It is assumed that the frequency of the subcarrier signal is 3579.545 KHz, and the frequency is divided by 1/4 by the frequency divider 10 to 894.886 KHz.
The signal is used as a clock signal by cylinder phase system power counter 1.
1 and divided by 1/16 223.722K
It is assumed that a Hz signal is supplied to the cylinder speed counter 12 as a clock signal.

The ratio of the count period of the cylinder phase system counter 11 and the count period of the cylinder speed system counter 12 during steady rotation is equal to the frequency ratio of the cylinder FC signal and the cylinder phase system force, which is 6 in the system configuration shown in FIG. Since the frequency ratio of the clock signals is 4, there is a difference of 24 times in the count amount per count period between the cylinder phase system counter 11 and the cylinder speed system counter 12.

Here, it is assumed that the precent value of the cylinder phase system counter 11 is Np, the count value at the time when the decoder 14 generates an output signal is Nf, and the precent value of the cylinder speed system counter 12 is Ns. Both the cylinder phase system counter 11 and the cylinder speed system counter 12 start counting down from the preset value, and during steady rotation, the cylinder phase system counter 11 passes through (00...000) and reaches Nf. In contrast, the cylinder speed counter 12 is precented at [00/old...OO].
Considering that the leading edge of the cylinder phase system force arrives near O] and re-presetting is performed, the following equation holds true.

That is, the cylinder speed system counter 1 is calculated based on the preset data Np for the cylinder phase system counter 11.
To obtain the preset data Ns for 2, the numerator on the right side of the +11 formula can be multiplied by 0.0417 (1/24). Specifically, the adder 39 in FIG. Perform the numerator operation and use the decimal multiplier 40 to
The calculation result is multiplied by 0.0417. By the way, the second
If you use the decimal multiplier shown in the figure, the multiplier data will be 16
It becomes (0555) in base number.

Now, during VTR playback, the capstan motor 23 rotates in synchronization with the cylinder motor 1, so the first
As shown in the figure, the capstan speed counter 28 can also receive preset data from the common memory 38 via an adder 39 and a decimal multiplier 41.
The idea behind this is cylinder speed counter 1, which has already been explained.
Since this is the same as in case 2, the explanation will be omitted.

By the way, in the embodiment shown in FIG.
An adder 39 and two decimal multipliers 40 and 41 are required in order to distribute precent data from the cylinder speed system counter 12 to the capstan speed system counter 28, but in reality, the system shown in FIG. can be realized by a microprocessor, and the adder 39.
Said fractional multiplier 40.41. The cylinder speed system counter 12. Starting with the capstan speed counter 28, the cylinder phase counter 11. The cabstan phase system counter 32 and its associated controllers are all realized by a program built into the microprocessor, or by a program that uses specific hardware (for example, an arithmetic logic unit) included in the microprocessor. Since it will be used, it will not be a big burden, and it will be highly flexible to change the specifications.The adder 39 can be made unnecessary by just changing the concept of the error detection part of the cylinder phase system a little. .

FIG. 3 is a block diagram showing another embodiment of the present invention, in which the decoder 14 in FIG. A comparator 42 is used for this purpose. Furthermore, in the device shown in Fig. 1, error detection data for the phase system and velocity system are each converted into analog values by separate D-A converters, whereas in the device shown in Fig. 3, the data is converted into analog values. The filter 43 or the digital filter 44 is configured to perform both filtering and synthesis of phase-based and velocity-based error detection data. Of course, the comparator 4
2. The functions of the digital filters 43, 44 can be realized by any microprocessor program.

Now, while the decoder 14 in FIG. 1 is provided to determine whether the count value of the cylinder phase system counter 11 has reached Nf, the comparator 42 in FIG. Compare the preset data Np of the cylinder phase system counter 11 supplied from 38 with the count amount after the cylinder phase system counter 11 counts down to [00...000), and when the two match. The cylinder phase system counter 11 is configured to send a re-precent command to the cylinder phase system counter 11. Therefore, when calculating the precent value Ns of the cylinder speed system counter 12 in the same way as the formula 111, the following formula is obtained.

That is, the cylinder speed system counter 1 is calculated based on the preset data Np for the cylinder phase system counter 11.
To obtain the precent data Ns for 2, set 0 to Np.
．． 0833 (1/l 2), and the adder 39 is not required in the device shown in FIG. 3. Furthermore, in the device shown in FIG. It is configured to be supplied from memory 38.

Effects of the Invention As is clear from the above description, the servo device of the present invention is suitable for rotating a rotating body such as the cylinder motor 1.

A phase error detection means (in the embodiment, the cylinder phase system counter 11) measures the phase difference between the inverted phase signal and the reference phase signal, and a speed error detection means (in the embodiment, the cylinder phase system counter 11) measures the repetition period of the rotational speed signal of the rotating body. In the example, a cylinder speed system counter 12), a driving means (cylinder motor drive circuit 22 in the example) that drives the rotating body by an error output signal obtained by combining the outputs of both;
memory means (
In the embodiment, it comprises a common memory 38) and a decimal multiplier (in the embodiment, a decimal multiplier 40) for multiplying the output data of the memory means by a decimal number smaller than 1 and supplying the result to the speed detection means. As a result, the data distribution mechanism for switching the rotational speed of the rotating body can be simplified more than ever before, and it is also possible to build a system that can flexibly respond to changes in specifications, contributing to system rationalization. It has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a servo device showing one embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration example of a decimal multiplier, and FIG. 3 is a block diagram showing another embodiment of the present invention. Diagram FIG. 4 is a block diagram showing a conventional example. 11...Cylinder phase system counter, 12. Old.
・Cylinder speed system counter, 22... Cylinder motor drive circuit, 38... Common memory, 39.
... Adder, 40 ... Decimal multiplier.

Claims (2)

[Claims] (1) A phase error detection means that measures the phase difference between the rotational phase signal of the rotating body and a reference phase signal, a speed error detection means that measures the repetition period of the rotational speed signal of the rotating body, and the outputs of both are synthesized. a drive means for driving the rotary body using an error output signal obtained by the rotational body, a memory means for supplying a plurality of reference value data for switching the rotational speed of the rotary body to the phase error detection means, and the memory means A servo device comprising decimal multiplication means for multiplying the output data by a decimal smaller than 1 and supplying the result to the speed detection means. (2) A phase error detection means that measures the phase difference between the rotational phase signal of the rotating body and the reference phase signal, a speed error detection means that measures the repetition period of the rotational speed signal of the rotating body, and the outputs of both are synthesized. a drive means for driving the rotary body using an error output signal obtained by the rotational body, a memory means for supplying a plurality of reference value data for switching the rotational speed of the rotary body to the phase error detection means, and the memory means A servo device comprising: an adding means for adding specific data to the output data of the adding means; and a decimal multiplication means for multiplying the output data of the adding means by a decimal smaller than 1 and supplying the result to the speed detecting means.