JPS59153480A - Detecting circuit - Google Patents

Abstract

PURPOSE:To accurately output a pulse width modulation signal without erroneous operation by providing a data relatching circuit. CONSTITUTION:A data relatching circuit 13 is provided between a data latch circuit 9 and a coincidence circuit 11, thereby once latching in the latch circuit 9 at the rising edge of a sampling pulse SP data based on quantized speed information. The data is relatched to the relatching circuit 13 by a signal P1 based on the carrier signal of pulse width modulation (PWM), thereby eliminating the generation of an erroneous coincidence signal from a coincidence circuit 11 at the altering point of the latched data D2 determined at the rising edge of the sampling pulse SP.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a velocity/phase detection circuit in a digital servo system.

[Prior art]

Generally, when controlling the motor rotation speed to a constant value,
As shown in No. 12, the frequency discrimination circuit 1 discriminates the frequency of the FG multiplied signal (frequency power generation signal) detected from the rotating disk 4 by the detector 50 in relation to the rotational speed of the motor 6, and A servo control method is employed in which an error voltage E is obtained, and this error voltage E is negatively fed back to the motor 6 via a motor drive amplifier 2 for control.

Incidentally, with the aim of increasing the degree of integration of the servo control circuit system and improving control performance, efforts are being made to perform digital processing using digital IC technology, which has been rapidly developing in recent years. In this digital method, the FG multiplied signal frequency detected in connection with motor rotation or the phase relative to a predetermined reference signal is measured using highly accurate clock pulses, and the error data obtained is digitally processed to perform pulse width modulation. (PWM) t, A method is generally used in which the output is demodulated by a low-pass filter and then a negative feedback control voltage is supplied to the motor.

The block diagram in FIG. 2 represents the frequency discrimination circuit 1 in FIG.
This shows a conventional example of digitizing. In FIG. 2, 5 is a pulse shaping circuit, 6 is a clock latch circuit, and 7 is a delay circuit.

8.10 is a counter, 9 is a data launch circuit, 11 is a coincidence circuit 14 is a differentiation circuit, and 12 is a pulse width modulation circuit. In FIG. 2, the sampling pulse SP obtained by shaping the pulse in the FG double signal pulse shaping circuit 5 from the terminal 15 and converting the clock pulse CP KN from the terminal 16 into the clock pulse from the terminal 16 by the chronoclutch circuit 6 is the clock pulse from the terminal 16. CI) is counted by counter 8 to obtain imofuko count data D,
is transmitted as a latch pulse to launch into the data latch circuit 9, and this sampling pulse SP is transmitted to the delay circuit 7.
The counter 8 is reset with a delayed signal SP in synchronization with the clock pulse CP. After the counter 8 is reset, the counter 8 starts counting the clock pulses CP again, and the reset pulse S by the next sampling pulse SP.
Counting continues until P' is input. That is, the count data D corresponding to the period (and hence the frequency) of the sampling pulse SP is latched in the data latch circuit 9. FIG. 6 shows a timing chart of the frequency discrimination circuit.

Next, in FIG. 2, the counter 10 outputs the clock CP.
is frequency-divided to obtain a carrier signal P of a constant frequency, and a differentiating circuit 14 forms a pulse P2 of a predetermined pulse width in synchronization with the clock CP from the rising edge of P. This pulse P is applied to the pulse width modulation circuit 12 as a carrier signal.
The output of the circuit 12 is sent to "H" by the pulse P2.

On the other hand, the output data D2 from the data latch circuit 9 and the count data number 29 of the counter 10 are compared in the coincidence circuit 11, and when the two match, a coincidence signal ID is sent to the circuit 11.
It is output from By this coincidence signal In, the output of the pulse width modulation port [12] is reset to -L''K.

Here, the time from when the pulse P2 is output until the coincidence signal ID is output, that is, the period during which the PWM output is "H", is proportional to the value of the output data D2 from the data latch circuit 9. There is. Therefore, as shown in Figure 6,
FG from terminal 15 using pulse P2 as a carrier signal
A PWM output that is pulse width modulated according to the value of the doubled signal frequency is obtained.

However, according to this conventional method, as shown in the timing chart of FIG. 6, when the content of the latch data D2 changes from A to B during the period (■), the coincidence circuit 11 Data D
2 and data D4 is not performed correctly, and an erroneous match signal is output at the data change, or the match signal is not output during this period, or is output at an undefined position, etc. As a result, the PWM output is (I), (in the loss period, a signal with a pulse width a corresponding to data 8 is continuously output, and in the period (1), a signal with a pulse width A corresponding to data B is output). should be output, but the pulse width a' is undefined in the period (■).
is output, and the PW that accurately reflects the magnitude of the FG frequency
There is a drawback that an M output cannot be obtained, which causes circuit disturbance and causes deterioration of control performance.

[Purpose of the invention]

An object of the present invention is to provide a velocity/phase detection circuit that accurately pulse width modulates quantized velocity 1 phase information in a digitally processed velocity/phase control device. It is in.

[Summary of the invention]

In order to achieve the above object, the present invention latches data based on the frequency or phase of the discriminated signal counted by the reference clock into a data latch circuit using a sampling pulse based on the discriminated signal, and then latches the data based on the frequency or phase of the discriminated signal counted by the reference clock. The latte data is latched again into the second data latch circuit in synchronization with the output from the frequency dividing circuit that divides the frequency.

Then, using the output from the frequency dividing circuit as a carrier signal, a pulse width modulation circuit is set in synchronization with this carrier signal, and the timing corresponds to the size of the re-latch data determined for each cycle of the carrier signal. The pulse width modulation circuit is reset by a pulse generated by the matching circuit. This prevents the pulse width modulation circuit from malfunctioning due to an erroneous matching pulse that occurs at the change in latch data, and also prevents malfunctions of the pulse width modulation circuit due to erroneous coincidence pulses that occur at the change in latch data.
It is configured to supply a PWM output that is accurately modulated according to the size of data.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 4 is a diagram showing an embodiment of the frequency discrimination circuit according to the present invention. FIG. 5 shows the timing chart.

In FIG. 4, circuit blocks that are the same as those in the conventional example of FIG. 2 are indicated by the same symbols as in FIG. First, the overall configuration will be explained. As explained in the conventional example, the FG double signal pulse shaping circuit 5
The clock latch circuit 6 latches the count data D1 from the counter 8 into the data launch circuit 9, and at the same time the SP signal The counter 8 is reset by a signal SP' which is slightly delayed. 1 is a data re-latch circuit that re-launches the output data D of the data latch circuit 9 by the output P from the counter 10. 11 is a match. In the circuit, counter 1
When the count data D4 of 0 and the output data D3 from the circuit 16 match, a match) pulse ■r is output. 12 is a pulse width modulation circuit that uses the Norculus P2 from the circuit 14 as a carrier signal. The present invention differs from the prior art in its configuration in that a data re-latch circuit 16 is provided between the data latch circuit 9 and the match circuit 11.

Next, the operation of the present invention will be explained using the circuit block diagram of FIG. 4 and the timing chart of FIG. 5.

First, as already explained in the conventional example, the count data D of the counter 8 is latched into the data launch circuit 9 at the rising edge of the sampling pulse SP formed based on the FG frequency. This latched data is expressed as latch data D2 in FIG. That is, the sampling pulse SP
As a result, latch data 1]2 changes from A to B.

Further, the data D2 from the circuit 9 is relatched by the data relatching circuit 16 at the rising edge of the output P from the counter 10.

As a result, the data re-latch circuit 13 outputs the latch data A every P,01 period as shown in the latch data D.
-, A-, B-, B-, B→... are determined.

Next, in the circuit 14, a pulse P2 is formed from the rise of the output P from the counter 10, and this pulse P2 sets the output of the pulse width modulation circuit 12 to 1-1'. At this time, the set operation using the pulse P2 has priority over the pulse ID Nyorori Cent operation, which will be described later.

When the latch data D3 from the circuit 13 and the count data D4 of the counter 10 match, the match circuit 11 outputs a match pulse 1. D is output, and this coincidence pulse ID resets the output of M12 to "L". This circuit 1
PWI from 2! Naturally, during the period when the vl output is “H”,
They are each proportional to the thickness of data A and B of latch data D3. Therefore, as shown in the PWM output 315 diagram, the pulse width a→b-, corresponding to the size of data A and B,
It becomes a pulse width modulation signal with a constant period T that changes as b.

As explained above, according to the configuration of the present invention, data can be easily added to the quantized velocity information using the sampling pulse B.
The data latch circuit 9 latches the data once at the rising edge of P, and the data is further latched based on the PWM carrier signal (
Since the data relatching circuit 16 is relatched by the signal P, an erroneous coincidence signal is generated from the coincidence circuit 11 at the data change point of the latch data D2 determined by the rising edge of the sampling pulse SP shown in the conventional example. There is no.

On the other hand, the data change point of latch data D3, for example,
In FIG. 5, when data A of data D3 changes to B in synchronization with pulse P, an erroneous coincidence signal Ix is sent to coincidence circuit 1.
1, the set operation by the pulse P in the circuit 12 has priority, so the reset operation by the erroneous coincidence signal Ix that occurs at the same time as this pulse P2 is not performed, and Ix is substantially It becomes invalid, and the PWM output from the circuit 12 maintains its normal state. Therefore, as a PWM output, data A-→B-, which is determined every -period T of the PWM carrier signal light P2),
Corresponding to B, the output is precisely pulse width modulated in proportion to the size of the data.

In the embodiment, the sampling data is obtained by counting the clock CP from the terminal 16 by the counter 8, and this same clock CP is inputted to the counter 10, but the present invention is not limited to this. Instead, the clock CP is used as a reference clock, zumbling data is counted with a first clock based on this, and a second clock based on the reference clock is divided by a counter 10 to a D1 constant frequency. In the embodiment, a frequency discrimination circuit that keeps the rotational speed of the motor etc. constant is shown, but a phase detection circuit that controls the rotational phase to be constant can also be realized with a similar configuration.

Furthermore, the present invention is applicable not only to speed/phase control devices for motors and the like, but also to a wide range of general digitally processed detection circuits.

〔Effect of the invention〕

As explained above, according to the present invention, in a speed/phase detection circuit that is digitally processed, a PW signal is modulated in accordance with the size of data including speed/phase error information.
When the present invention is applied to a motor servo control circuit that can accurately output M4 without malfunctioning, a system with extremely good control performance can be realized.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the motor speed control device, I'
! 2 is a block diagram showing a conventional example of a digitally processed frequency discrimination circuit, FIG. 6 is a timing chart thereof, and FIG. 4 is a block diagram of an embodiment of a digitally processed frequency discrimination circuit according to the present invention. FIG. 5 is a timing chart thereof. 8 Counter, 9 Data launch circuit, 10 Counter, 11 Match circuit, 12 Pulse width modulation circuit, 13 Data re-latch circuit, 14... Differential circuit. Representative Patent Attorney Akira Ko<,'

Claims (1)

[Claims] 1. A first data latch circuit that latches data based on the frequency or phase of the signal to be discriminated, counted by a first clock based on the reference clock, using a sampling pulse based on the signal to be discriminated; a frequency dividing circuit that divides the second clock to a predetermined frequency; and a second frequency dividing circuit that re-launches the output data from the first data latch circuit in synchronization with the output of the frequency dividing circuit.
a data latch circuit, which sets (or resets) the output from the frequency dividing circuit as a carrier signal in synchronization with the carrier signal, and the size of the data latched by the second data latch circuit. A detection circuit characterized in that a pulse width modulated output is obtained by resetting (or cent) using a coincidence pulse generated at a timing corresponding to the detection circuit.