JPH0628830Y2 - PWM signal generation circuit - Google Patents

Description

Detailed Description of the Invention A. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM signal generation circuit that generates a PWM signal according to digital data.

B. SUMMARY OF THE INVENTION In generating a PWM signal including a synchronizing signal, the present invention sets a flip-flop before the counter having a count value larger than the maximum value of data reaches the maximum count value, and flip-flops when they match the value of the data. Reset, and obtain a PWM signal at the output of the flip-flop, a PWM including a sync pulse without complicating the circuit configuration.
Is what you get.

C. Conventional technology In devices that use servo motors such as industrial robots,
The controller gives a current command to the servo driver, and the servo driver performs feedback control of the servo motor. Such as servo control system,
In a device in which a driver drives an electric device such as a motor according to a command given from a controller, it is excellent in insulation and noise resistance that a digital signal is used to exchange a command signal between the controller and the driver. Suitable for using a digital computer for the controller.

FIG. 3 shows a conventional circuit that generates a signal having a pulse width according to the output data of the controller when a PWM signal is used to exchange signals between the controller and the driver. The counter 1 counts the clock pulses from the clock generation circuit 2 and outputs each bit digit output to the equivalent comparator 3
And the overflow output to the flip-flop 4 set input. The equivalent comparator 3 compares the digital data DATA from a controller (not shown) with the other comparison input and this input data with the data from the counter 1, and when both match, a reset input is given to the flip-flop 4. A PWM output having a pulse width corresponding to the data DATA is obtained as the Q output of the flip-flop 4.

FIG. 4 shows a PWM output waveform diagram, where one cycle T ₀ of the counter 1 becomes the PWM output cycle, and the counting period T _D of the counter 1 from the overflow of the counter 1 to the coincidence with the value of the data DATA Becomes the PWM pulse width.

D. Problems to be Solved by the Invention In the conventional circuit, when the data DATA becomes the minimum value (zero) or the maximum value (the maximum count value of the counter 1), the PW
M output remains "0" or "1"
There is a problem that the signal processing on the driver side that receives the WM output cannot be synchronized, and an erroneous protection operation such as a failure of the PWM transmission system occurs.

In order to solve this problem, it is conceivable to apply a synchronization pulse in addition to the PWM waveform, but at this time, the driver side needs a processing circuit for distinguishing the synchronization pulse from the PWM signal, and the driver side configuration is required. There was a complication.

E. Means and Actions for Solving Problems The present invention has been made in view of the above problems, and provides a counter for counting clocks and digital data whose maximum value is lower than the maximum count value of this counter. The
An equivalent comparator for detecting a match between this data value and the count value of the counter, and a match detection of the equivalent comparator set when the counter has a value smaller than the maximum count value and larger than the maximum value of the data. And a flip-flop which is reset by means to obtain a pulse width modulated output including a sync pulse, and which generates a sync pulse which changes the logic level at the set point of the flip-flop with the data maximum value to the counter maximum count value as the synchronization period.

F. Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. 3 is different from FIG. 3 in that the maximum count value of the counter 5 is made larger than the maximum value of the data DATA, and the set of the flip-flop 4 is made larger than the maximum value of the data DATA and smaller than the maximum count value. The equivalent comparator 6 compares the same number of bits as the counter 5 with the upper bit "0" of the data DATA as a fixed value.

In this configuration, for example, BCD as data DATA
When values 0 to 99 of two rows are given, the counter 5 is a 120-ary counter, and the flip-flop 4 is set by the count value 110 of the counter 5. According to this example, when the count value of the counter 5 reaches 0 to 100 and the data DATA matches, resetting is given to the flip-flop 4 from the equivalent comparator 6, and then the count value of the counter 5 reaches 110. Then, the flip-flop 4 is set, and then the flip-flop 4 is set when the value of the next data DATA is again matched after the counter 5 overflows.

Therefore, the count value of the counter 5 and the PWM output have a relationship as shown in FIG. 2, the maximum count value of the counter 5 becomes the cycle T ₀ , and the data DAT starts when the counter 5 overflows.
Period _{T D} until matching A value corresponds to a data value, the time period _{T D} is the minimum value becomes the maximum value 99 from 0, the period _T is the _S count 110 from the count value 100 of the counter 5 to 120 A sync pulse that changes from logic "0" to "1" is generated at the boundary. This synchronizing pulse is always given at the timing and pulse width synchronized with the counter, although the data DATA changes from the minimum value 0 to the maximum value 99.
The synchronization processing can be performed by taking in the PWM output including the synchronization pulse on the driver side.

In the embodiment, the data is not limited to BCD and may be in another code format. In addition, the same operational effect can be obtained by appropriately changing the design such that the counter is a subtraction counter.

G. As described above, according to the present invention, the maximum count value of the counter is made larger than the maximum value of the data, the flip-flop is set by the count value in the meantime, and the flip-flop is reset when the data value matches. Since the PWM output including the sync signal is obtained by P, the P including the sync signal can be obtained only by increasing the number of digits of the counter and the comparator of the conventional circuit.
There is an effect that a WM signal can be generated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a conventional circuit diagram and FIG. 4 is a conventional PWM waveform diagram. 1, 5 ... Counter, 2 ... Clock generator, 3, 6 ... Equivalent comparator, 4 ... Flip-flop.

Claims (1)

[Scope of utility model registration request] 1. A counter that counts clocks, and an equivalent comparator that receives digital data whose maximum value is a value lower than the maximum count value of the counter, and that detects a coincidence between this data value and the count value of the counter. , A flip-flop that is set when the counter reaches a value smaller than the maximum count value and larger than the maximum value of the data and reset by coincidence detection of the equivalent comparator to obtain a pulse width modulation output including a sync pulse. A PWM signal generation circuit characterized by being provided.