JPS6255714A - Revolution controller - Google Patents

Abstract

PURPOSE:To prevent an error produced from an error signal by using means to produce the 1st speed error signal, an input capture register to store the count value a counter, a means to produce the 2nd speed error signal and a means to keep the processing of the 2nd speed error signal producing means in a waiting state. CONSTITUTION:A timer counter 150 counts the reference clock signals and is reset or preset with the timing of a reference phase signal. The 1st speed error signal producing means 151 produces the 1st rotation control signal (the 1st speed error signal) based on the count value of the counter 150 and with the timing of the 1st revolution detecting signal (the 1st GF signal, i.e., the FG signal of a head motor). An input capture register 152 stores the the count value of the counter 150 with the timing of the 2nd revolution detecting signal (the 2nd FG signal, e.g., the FG signal of a capstan motor). The 2nd speed error signal producing means 153 supplies the 2nd revolution detecting signal and produces the 2nd revolution control signal (the 2nd speed error signal) based on the value stored in the register 152. A priority means 154 gives the higher priority to the processing of the means 151 than the processing of the means 152 and keeps the processing of the means 152 under a waiting state.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a rotation control device for controlling a plurality of motors.

(b) Prior Art Digital servo devices have come to be used to control the rotation of motors included in video tape recorders (VTRs) and the like.

The conventional digital servo device is described in Matsushita Technical Report VOL, 28. No, 3. June, 198
As shown in Figure 25 on page 191 of 2 and Figure 26 on page 192, one motor is configured using two counters, one each for speed control and phase control. has been done.

Next, a conventional general digital servo device will be described with reference to the block diagram shown in FIG. (1)
is the motor to be controlled, and the speed detection pulse generation circuit (
1a) and a phase detection pulse generation circuit (1b). The first counter (2a) is a reference clock signal generation circuit (
3), and counts the output of the speed detection pulse generation circuit (1).
Synchronizing with the output (FG pulse) of a), the count value is
The analog output of the first D/A converter (3a), which is output to the D/A converter (3a) and reset (see Figure 10), is sent to the first sample and hold circuit (until the next FG pulse rises). 4a) and is input to the adder (5>) as a speed error signal. On the other hand, the second counter (2b) synchronizes with the output (V pulse) of the phase reference signal generator (6>) and receives the reference clock signal δ. The counting of the output signals of the signal generator (3) is started, and in synchronization with the output (PG pulse) of the phase detection pulse generating circuit (1b), the counted value is transferred to the second D/
It is output to the A converter (3b) and reset (11th
(see figure), the analog output of the second D/A converter (3b) is held in the second sample and hold circuit (4b) until the next PG pulse rises, and is input to the addition!! (5) as a phase error signal. The output of the adder (5) is input to a drive circuit (7) to control the motor (1).

However, when a digital servo device as described above is constructed using a one-chip microcomputer, the microcomputer has one or two counters in one chip.
Usually, only one motor is built-in, so one chip has the disadvantage that it can control the speed and phase of at most one motor. That is, in order to control a plurality of motors, the number of microcomputers must be increased according to the number of motors.

Therefore, the applicant of the present application has previously proposed a configuration in which the rotation of a plurality of motors can be controlled using one counter (Japanese Patent Application No. 59-214954).

Next, this configuration will be explained. The block diagram of the digital servo device for the heradmorph and capstan motor of smnv'rR, that is, the two motors, is shown in the 12th block diagram.
In the figure, (30) is a Herad motor, which is equipped with a speed detection pulse generator (30g> (output is FGH pulse) and a phase detection pulse generator (30b) (output is PGH pulse). (31) is Similarly, with the capstan motor, the speed detection pulse generator (31a) (output is FCC pulse)
and a phase detection pulse generator (31b) (output is PGC pulse) as 0 phase reference signal (V pulse).
During +mVTH recording, a 30Hz signal is obtained by dividing the output of the synchronization separation circuit (32), which separates the vertical synchronization signal from the video signal, by a frequency divider (33), and when reproducing it, a crystal oscillator
34〉 output divided by frequency divider (35) to 30Hz
switch (36) depending on the recording or playback mode.
) and input it to the counter (37). The counter (37) counts the signal from the reference clock signal generator (38) and is reset in synchronization with the V pulse (see A in FIG. 11).

The speed control and phase control of each motor is performed by the counter (37).
This is done by sharing the The speed error signal of the digital value of the head motor (30) is generated by two latch circuits (
391) (392), the two latch circuits (391)
Comparator (40) that compares the value latched in (392)
, the FGH pulse and the V pulse are input, and the digital value phase error signal is generated by a controller (41) that controls the comparator (40) in consideration of the reset of the counter by the V pulse, and is synchronized with the PGH pulse. and counter (3)
7) is produced by a latch circuit (42) that reads the count value. On the other hand, the digital value speed error signal of the cab stan motor (31) is synchronized with the FCC pulse by the counter (
Two latch circuits (43) that sequentially read the count values of (37)
1) Comparator (4) that compares the value latched to (432)
4) With the FGC pulse and V pulse as input, taking into account the reset of the counter by the ■ pulse, after the ■ pulse is generated, N4 + NM- at the rising edge of the next FG pulse.
A digital phase error signal is generated by the controller (45) that controls the comparator (44) so as to calculate N3, and the latch circuit reads the count value of the counter (37) in synchronization with the PGC pulse. It is created by (46).

The error signal of each digital value is sent to a multiplexer (47)
, a D/A converter (48), and a demultiplexer (49) into analog values, which are held in each sample and hold circuit. That is, the output of the comparator (40) is D
/A conversion and is controlled by the FGH pulse as a speed error signal for the head motor (30). The output of the latch circuit (42) is D/A converted into a sample hold circuit (50a), and a comparator is connected to a sample hold circuit (50b) which is controlled by a PGH pulse as a phase error signal of the head motor (30). The output of (44) is D/A converted and sent to a sample hold circuit (51a) controlled by FGC pulses as a speed error signal for the capstan motor (31).
The output of the head motor (31) is D/A converted.
) are held as phase error signals in a sample and hold circuit (51b) controlled by PGC pulses. The multiplexer (47) and demultiplexer (49) are supplied with FGH pulses, PGH pulses, FGC pulses, and PGC VALSCA III control signals, respectively, and the error signals of each digital value are sent to the D/A converter by time division. (48) is shared.

Both the speed error signal held in the sample and hold circuit (<50a) and the phase error signal held in the sample and hold circuit (50b) are sent to the adder (52) and the drive circuit (
53) to control the head motor (30);
(50 is a starter, which sends a start signal to the drive circuit (53) via the adder (52) at the time of starting.

On the other hand, the speed error signal held in the sample and hold circuit (51a) and the phase error signal held in the sample and hold circuit (51b) are both sent to the capstan motor (31) via an adder (55) and a drive circuit (56). (57) is a starter, which sends a start signal to the drive circuit (56) via the adder (55) at the time of starting.However, the above is the case when recording on an 8mm VTR, and during playback. In order to use the output of the pilot IC (5g) as a phase error signal for the capstan motor (31), it is necessary to switch it with a switch (59).This pilot IC (5g) records each video track of the tape. This system generates a tracking control signal based on the four pilot signals.
Control using this pilot signal is described in Japanese Patent Application Laid-Open No. 53-1161.
It is detailed in No. 20.

FIG. 4 shows the FGH pulse when the head motor and capstan motor are at the set speed and set phase, respectively.
The outputs of the PGH pulse, FGC pulse, and PGC pulse are shown, with the horizontal axis representing time and the vertical axis representing the magnitude of the output.

In the above configuration, the output of the counter (37) reset by the reference signal is latched at the FG flaw signal PG times signal timing. In speed control, Carantuff 37) is latched at two consecutive FG scratch signal timings.
In the 0 phase control that compares the data of the counter (37), the data of the counter (37) is latched and used with a PG pulse having the same period as the reference signal.

The above-mentioned configuration is suitable for constructing using a micro combi coater. In other words, it is sufficient to have only one counter. Further, latching of counter (37) data, comparison processing, etc. can be completed by software.

When constructing a digital servo device using a microcomputer, processing is performed according to a program. Therefore, the phases of each FG flaw signal and PG multiplication signal must not be the same. In other words, when the cylinder motor's FG flaw signal and the capstan motor's FG flaw signal occur at the same time or very close to each other, Processing is performed on the signal or signal with a high priority, and processing on other signals is not performed until the processing is completed.Therefore, the signal timing for other signals is the same as if the signal timing was delayed, and the error signal created has an error.

Let's consider the above phase relationship regarding an actual VTR. During recording, the capstan motor only needs to rotate at a certain speed, so if you select the FG flaw signal frequency appropriately, you can prevent the FC (No. 6, PG double signal from being input to the microcomputer at the same time). I can do it.

However, during playback, since tracking control is performed, the phase of the capstan motor relative to the reference signal cannot be fixed, so there is a possibility that the 2018 PG double signal is input to the microcomputer at the same time or very close to each other.

(c) Problems to be solved by the invention: FG flaw signals of two motors, PG multiplied signals cannot be input to the microcomputer at the same time, and the created error signal may contain errors, causing errors in motor rotation control. There is.

(d) Means for Solving the Problems The present invention provides a counter that counts the reference clock signal and is reset or preset by the phase reference signal, and a counter that counts the reference clock signal and is reset or preset by the phase reference signal, and as a first FG multiplier signal input, the timing of the FC signal is calculated. means for creating a first speed error signal based on the counted value of a counter; an input capture register that receives a 20th FG signal as an input and stores the counted value of the counter at the second FG multiplied signal timing of the machine; and the input capture register; means for creating a second speed error signal based on a value stored in a register, and the processing of the first speed error signal creation means is given priority over the processing of the second speed error signal creation means, and the second speed error signal is and means for waiting for processing by the creation means.

(E) Effect Regarding the second FC signal, since the count value of the counter is stored in the input capture register, the first FC signal
Even if the processing related to the G signal is prioritized, no error occurs in the speed error signal based on the second FG signal.

(f) Examples The present invention will be explained in detail below.

FIG. 2 is a block diagram showing an embodiment.

(toe) is a microcomputer, HD6301
are using. (lot) is Herad motor, (10
2) is the capstan motor, (101a) is the FG signal detection means of the herad motor (101), and (102a) is the FG signal detection means of the capstan motor (102>).

(103) to (106) are microcomputers (10
(107) is the first to fourth D/A converters that D/A converts the output from Ai inverter (107).
03) (104) Output adder, (108) first phase compensation circuit, (109) third and fourth D/A converters (
105) and (106) are output adders, and (110) is a second phase compensation circuit.

<111) is the input terminal for the AFT error signal, and D/
Depending on whether the A funverter (106) output and AFT error signal are in recording mode or playback mode,
12).

The microcomputer (10G) has RAM (1
13) ROM (114), CPU (115), output port (116) (117) (118) (119),
16-bit timer counter (120), input capture register (121), output conveyor register 1.2 (122) (123), data bus (12
4) etc.

This microcomputer (100) has three external interrupts (NMI, IRQt, IRQt) and seven internal interrupts. Then, the phase reference signal (vertical synchronization signal of the video signal during recording, 30Hz reference signal during playback) is connected to the NMI (non-mascarable interwoven) terminal (
125), the FG double signal IR of the head motor (107)
Ql (interconnected request 1) terminal <126),
Capstan motor (102) FG double signal ICI (input key interrupt) terminal (127) (P
2-o, pin 9). There is also an 0CI (output conveyor increment) based on the outputs of the comparison means (128) and (129).

Incidentally, as is well known, interrupts are performed by hardware, and priorities are determined for various interrupts. In the HD6301X, among the above interrupts, NMI has the highest priority, IRQs, ICI, QC17)
In addition, if the microcomputer is already in an interrupt operation when the interrupt instruction is completed, a new interrupt operation is performed after this operation is completed.

In this microcomputer (10G), IC!
When the level of the terminal (127) changes (the direction of change can be set by the program), the count value at that time of the timer counter (free running counter that counts the reference clock signal) (120) is stored in the input capture register (12).
1) can be maintained. At the same time, an ICI interrupt request is also made.

The output conveyor pair interface (OCI) is the output conveyor register 1. set by the program.
An interrupt request is internally generated when the value of 2 (OCRI, 2) (122) (123) matches the contents of the timer counter (120).

Next, the operation will be explained. Flowcharts are shown in FIGS. 3 to 7, and FIG. 8 is a waveform diagram for explaining the operation. When the microcomputer (100) is initialized, the microcomputer (100) enters an interrupt wait state. Then, when an interrupt request is made, the corresponding processing is performed, and when the processing is completed, the CPU enters the interrupt waiting state again.

The phase reference signal input to the terminal (125) (Fig. 8(b)
)) falls, NMI is requested. Then, the timer counter (120) is set to a predetermined value (reset in the embodiment, FIG. 8(a)), IRQ1% ICI is permitted, and mask data is set to OCR1 (122).

When the head motor FG multiplied signal C) is input to the IRQr terminal (126), an IRQl interrupt is requested.

At this time, the data of the timer counter (120) and the data of the timer counter (120) of the previous FG multiplication signal (R
A M (fully stored in 113)) is read out, a calculation is performed between the two, a speed error signal is created, and it is output to boat A (116).

The current data is then stored in the RAM in preparation for the next process.

The phase error signal is created by utilizing the fact that the FG multiplied signal and the PG multiplied signal have a predetermined relationship. In other words, a signal obtained by dividing the frequency of the FG multiplied signal at a predetermined timing can be used as a PG multiplied signal. Although not shown in FIG. 2, the head motor (100) is connected to the input port of the microcomputer (100).
107), and when there is an IRQI request, if the PG double signal is input to this input port, the data of the timer counter (120) at this time is sent to boat B as a phase error signal. Another interrupt (IRQ2) may be used to create the 0 phase error signal output to (117).

A speed error signal and a phase error signal are created and outputted.6.
! : Enable ICI, set the next mask data in OCR2 (123), and return to interrupt wait state.

IC! When the capstan FG signal (h) is input to the terminal (127), the data of the timer counter (120) can be held in the ICR (121) as described above, and if no other interrupt operation is being performed. , the ICI interrupt is executed. Then, a speed error signal is created based on the data in the ICR (121) and the data in the RAM (113), and outputted to the boat C (118>.
The 0 phase error signal that causes ICR (121) to be stored in (113) for next processing can be used only during recording. Therefore, the frequency of the FG multiplied signal is divided a predetermined number of times and used. ICR when the FG multiplied signal is input a predetermined number of times
A phase error signal is created based on the data of (121) and output to boat D (119).

Connect the capstan motor (1
If the microcomputer (10G) is in the middle of another interrupt operation when the FG multiplier signal h) of 02) is input, the interrupt is awaited until the end of the operation. However, F
Since the data of the counter (120) at the timing of the G multiplication signal h) is held in the ICR (121), even if the interrupt operation of tCt is performed after the previous interrupt operation is completed, the speed error signal will be created correctly. Ru.

In the above explanation, a case has been described in which the FG multiplied signal h) of the capstan motor (102') is generated after the phase reference signal (b) and the FG multiplied signal C) of the head motor (101). However, the capstan motor (1G2
) is input to the microcomputer (100) at a slightly earlier timing than both signals (b) and (c), other interrupt processing must wait until the 101 interrupt processing is completed. , in this case, there will be some inconvenience.

Therefore, the time required for IC1 interrupt processing (for example, 30
ICI interrupts are masked during a period that precedes the phase reference signal (b) and head motor FG signal (C) by 0 to 500 μ5 ec) (or a slightly longer time).

This mask operation includes 0 CRI, 2 (122) (123
> and OCI. In NMI processing, 0CR1
If count value A is set in (122), OCI is requested every time the data of timer counter (12G>) becomes equal to A (Fig. 8(d)), and as shown in Fig. 7, I
RQs and ICI will be suspended.

On the other hand, in IRQI processing, predetermined data before the next IRQt interrupt timing is set in OCR2 (123). Then, the contents of the timer counter (120) and the OC
Every time the contents of R2 (123>) match, OCI is requested (FIG. 8(r)), and ICI is prohibited.

The disabled interrupt processing is re-enabled when the NMI and IRQ1 processing is completed (FIGS. 4 and 5).

Therefore, the interrupt priority and 0CRI, 2 (122
) (123>), the IRQl interrupt is masked during the H level period (FIG. 8(d)), and the I
The CI interrupt is masked during the H level period shown in FIGS. 8(d) and (g). When using a microcomputer without OCI, other priority means may be provided.

The FG multiplier signal h) of the capstan motor (102) is supplied to the ICI terminal (127) because the rotation of the cylinder motor (101) is controlled to be locked to the phase reference signal (b). However, the capstan motor (102
) changes due to tracking control.

Further, although the above embodiments are processed using FG signal, it can also be applied to PG signal. It is also conceivable to add the phase error and velocity error signals within the microcomputer and output them via a digital filter based on a program.

The operation of the microcomputer (100) described above can be expressed in terms of functions as shown in FIG. 1 in a block diagram. The timer counter (150) counts the reference clock signal and is reset or preset at the timing of the reference phase signal. (151) is means for creating a first rotation control signal (first speed error signal) based on the count value of the timer counter at the timing of the first rotation detection signal (first FG signal, that is, the FG multiplication signal of the head motor. 152) is the timer counter (150) at the timing of the second rotation detection signal (second FG signal, that is, the FG multiplication signal of the capstan motor).
an input capture register that stores the count value of
(153) inputs the second rotation detection signal and outputs the second rotation detection signal based on the stored value of the input capture register (152).
means for creating a rotation control signal (second speed error signal);
154) is a priority means for giving priority to the processing of the first rotation control signal generation means (151) over the processing of the second rotation control signal generation means (152) and making the processing of the second rotation control signal generation means (152) wait. It is.

(G) Effects of the Invention As described above, according to the present invention, in a rotation control device that controls the rotation of two or more motors, the motor rotation detection signal (PG multiplied signal, FG multiplied signal Even if the rotation detection signal of another motor overlaps or occurs close to each other, the count value of the other motor is stored in the input capture register, so there is no risk of an error occurring in the error signal, so it is effective. be.

[Brief explanation of the drawing]

Figure 1 is a functional block diagram of the present invention, Figure 2 is a circuit block diagram of an embodiment, Figures 3, 4, 5, 6, and 7.
The figure is a flowchart, Figure 8 is a diagram showing the operation, Figure 9,
FIG. 12 is a circuit block diagram showing a conventional example, and FIGS. 10, 11, and 13 are waveform diagrams of the conventional example. (150)...Counter, (151)...First error signal creation means, (152)...Input capture register, (153)...Second error signal creation means,
(154)...priority means.

Claims (1)

[Claims] (1) A counter that counts the reference clock signal and is reset or preset by the phase reference signal, and a first error based on the count value of the counter at the timing of the first rotation detection signal with the first rotation detection signal as input. a first error signal creation means for creating a signal; an input capture register for storing the counted value of the counter at the timing of the second rotation detection signal; a second error signal generating means for generating a second error signal based on the second error signal generating means; A rotation control device comprising a priority means for waiting processing.