JPS63234889A - Phase controlling circuit - Google Patents

Abstract

PURPOSE:To enable the pull-in time of a phase controlling system to be shortened, by modulating a rotational speed according to the generating position of pulse signal showing rotary phase when the rotational speed is set to be almost constant. CONSTITUTION:The input of FG signal to a terminal 401, the input of reference signal to a terminal 402, and the input of H.SW signal to a terminal 403 are respectively provided. By input capture registers 404-406, at the time of the rise or the fall edge of the respective signals of the terminals 401-403, the count value of a counter circuit 407 is latched. A microcomputer 410 is composed of a central processing unit 411, a ROM 412, a RAM 413, and an interruption handling circuit 414. So far as the micro-computer 410 is concerned, by using a value latched by the respective input capture registers 404-406, arithmetic is performed on speed error signal and phase error signal, and both the signals are combined with each other, and after that, the signals are filter- processed, and its result is fed to a motor driving circuit via a D/A converter circuit 415.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to phase control circuits, and more particularly to a novel phase control circuit that reduces the pull-in time of a phase control system.

Conventional technology The application of controlling the speed and phase of a controlled object to a constant value is wide-ranging, but here we will explain it using a two-head helical scan type magnetic recording/reproducing device (hereinafter referred to as a VTR) as an example. do.

In a VTR, it is necessary to rotate a rotating cylinder containing a video head at high speed in order to set the recording wavelength of the video signal to a practical value on the magnetic tape. The rotational speed of the rotary cylinder is controlled by a speed control circuit so that the rotational speed is approximately constant, and the rotational phase is controlled so that the phase difference from the reference phase signal is a constant value.

FIG. 15 shows a part of the speed and phase control circuit in a conventional VTR. In the same country, a terminal 1501 receives a signal from a frequency generator (FG) that generates a signal with a frequency proportional to the rotational speed of a rotating cylinder. is input. F
0 circuits 1503 and 1 which measure the period in the G multiplied signal speed error signal generation circuit 1502 and output the amount of difference between the FG multiplied signal period and the reference period as a speed error signal.
508 is a pulse width modulation circuit (PWM circuit), which is a type of D/A converter that outputs a signal having a pulse width corresponding to an input digital signal value.

Therefore, the speed error signal is outputted to the terminal 1504 as a PWM signal.

A reference signal is input to a terminal 1505, and a head switching signal (H, SW) is input to a terminal 1506. Here, the reference signal is a signal obtained by separating and extracting a vertical synchronizing signal included in a video signal when recording a video signal, and is a 60 Hz pulse signal in the case of an NTSC VTR. The H3SW signal is a signal that indicates the rotational phase of the rotating cylinder, and is 30H for an NTSC VTR.
z rectangular wave signal. The phase difference between the signal frequency-divided to the reference signal t-1/2 and the H and SW signals is extracted by a phase error signal generation circuit 1507, and the extracted phase error signal is D/A converted by a PWM circuit 1508. and terminal 150
9 is output.

Each PWM signal output to terminals 1504 and 1509 is smoothed by a resistor R, a capacitor C, and FL2 and 02, respectively, and converted into an analog signal. Further, the speed error signal and the phase error signal are combined by a resistor R3. The ratio (mix ratio) at which the phase error signal is combined with the speed error signal changes depending on the value of the resistor R3. This mix ratio is usually a few times smaller to ensure the stability of the phase control system.
It is selected to be one in tenths of the total. The composite value of the velocity and phase error signals obtained at m-child 1510 is supplied to a drive circuit of a motor that drives the rotary cylinder, and controls the rotational speed and rotational phase of the rotary cylinder.

FIG. 16 shows a more detailed block diagram of a conventional phase comparator circuit, and FIG. 14 shows waveforms at various parts in FIG. 16. In both figures, the same symbol indicates the same signal. The reference signal (vertical synchronization signal) (14a) input from the terminal 1601 is frequency-divided by the 1/2 frequency divider circuit 1602, and the signal (14b') is 0. The circuit 1603 is a preset circuit, and sets a predetermined preset value in the counter circuit 1604 at the timing of the rising edge of the signal (14b).

The counter circuit 1604 starts counting from a preset value, and when the counter overflows,
Counting starts again from the preset value. Therefore, the output value of the counter circuit 1604 is
) Repeat the changes shown.

By changing the preset value, the cycle shown in FIG. 14 1401 can be changed, so the stable position of the phase of the controlled signal can be adjusted by changing the preset value.

Circuits 1607 and 1608 are circuits that apparently limit the upper and lower limits of the output value of the counter circuit 1604, and the upper limit value limiting circuit 1607 controls the counter output (14c) from the rising edge of the signal (14b). The number of overflows is counted, and when this number exceeds a certain value, the value of the latch circuit 1605 is held at the maximum value indicated by 1402. Further, the lower limit circuit 1608 holds the value of the latch times 81605 at the minimum value indicated by 1403 when the number of overflows is less than a certain value. Therefore, the counter output (14c) supplied to the latch circuit 1605 is apparently the same as the counter output indicated by the signal (14d)'Q. terminal 16
The H, SW signal (14e) is input from 06, and the counter output (14e) is output at the timing of the falling edge of this signal.
4d) is latched. An output 1609 of the latch circuit 1605 is supplied to a PWM circuit 1508 shown in FIG. 15, and output as a phase error signal.

Problems to be Solved by the Invention In the phase comparator circuit with such a conventional circuit configuration,
There is a problem in that the phase pull-in time during a transient is limited depending on the power supply voltage and mix ratio. This is because the lower limit value of the phase error signal output from the terminal 1509 in FIG. 15 is the ground potential, and the upper limit value is the power supply voltage value. Then, the level of the difference between this upper limit value and lower limit value is
Corresponds to the range in which the rotational speed is modulated. The larger the modulation range, the larger the amount of change in rotational speed, and the faster the speed at which the phase changes. That is, the time required to move from a position where the phase is constant and deviated to a stable point becomes faster. However, the modulation range is limited by the power supply voltage and further limited by the mix ratio.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel phase comparator circuit in which the phase acquisition time is not limited by the mix ratio and can shorten the phase acquisition time.

Means for Solving the Problems In order to solve the above problems, the present invention includes modulation means for modulating the rotational speed, and the modulation means has a constant phase difference between the phase reference signal and the controlled signal. When the amount of the phase error signal is within the phase error range, the amount of the phase error signal is configured to change in proportion to the phase difference, and when the phase difference is outside the fixed phase range, the amount of the phase error signal changes at the current phase comparison timing of the controlled signal. In the period between t and the phase comparison timing of the next controlled signal, n, there is a period in which the rotation speed is accelerated or decelerated compared to the rotation speed at time t, and a period in which the rotation speed at a steady state is maintained. and a period of t.
The level of acceleration or deceleration is set so that the amount of change in the rotational phase n in the time from t to t corresponds to one cycle of the rotational phase of the controlled signal during steady rotation.

Effect of the Invention With the above configuration, the present invention sets the generation position of the next controlled signal to a stable position of the phase control system, and also sets the rotational speed at the generation position of the next controlled signal to the rotational speed in a steady state. As a result, the phase control system is opened when it is pulled in!
Since this can be done in one cycle of the lI# signal,
It is possible to shorten the phase pull-in time during transition.

Embodiments Before describing specific embodiments of the present invention, the relationship between the configuration of the phase comparator circuit and the phase pull-in time will be explained first. FIG. 13 is a diagram showing the relationship between two types of phase error signal amounts and controlled signals. In the figure, the signal (13a
) shows the change in the amount of phase error signal with respect to the amount of phase shift from the reference signal, the signal (13b) shows the controlled signal, the horizontal axis is time, and the signal (13a) is synchronized with the rotational phase of the reference signal. ing. For example, the rotational phase of the controlled signal is t5o.
When it is at the position indicated by t51, the amount of the phase error signal is the amount indicated by 1301, and when it is at the position indicated by t51, the amount of the phase error signal is the amount 1302. It is assumed that the phase control system is stable when the phase error signal is an amount indicated by 1301.

When the power is turned on, the rotation speed of the motor is gradually accelerated from a stopped state, and the speed control circuit controls the rotation speed to a nearly constant speed, and the phase control circuit keeps the rotation phase and the reference signal constant. controlled by. Now, when the rotational speed of the motor reaches a predetermined speed, the reference signal and the rotational phase of the rotating cylinder are as shown in FIGS. 13(13a) and (1).
It is assumed that the relationship t51 shown in 3b) exists. At this time,
Assuming that the rotational speed of the rotating cylinder exactly matches the target rotational speed, a pulse signal 1303 indicating the rotational phase is generated at a position indicated by 1304 after a certain period of time (time equivalent to one cycle). do. In other words, the signal (13a) synchronized with the phase of the reference signal and the pulse signal 1303
The relative positional relationship with 1304 and 1304 does not change, but in reality, the rotational speed is accelerated by the phase error amount 1302 obtained at time t51, and a pulse signal is generated at the position indicated by 1305 after a certain period of time. become. By repeating this operation, the controlled signal (
The pulse generation position 13b) becomes stable after moving to the center of the slope of the signal (13a) (a position corresponding to the position indicated by 1301). Then, the value of the phase correction amount 1306 that moves after a certain period of time is the phase error signal amount 13
It is determined by the amount of change in the rotational speed that can be changed by 02.

The signal shown in FIG. 13 (13c) has a level other than the part (hereinafter referred to as a proportional slope part) where the amount of the phase error signal changes proportionally according to the phase difference shown in (13a).
This shows the amount of phase error when the signal level is made larger or smaller than the signal level shown in . When using a method of handling velocity and phase error signals numerically and mixing them as described below, such a level selection can be made freely as long as there is no overflow of the numerical values that can be handled.

The signal (13d) indicates the controlled signal. The stable point of the 0-phase control system is when the pulse signal of the controlled signal is located at the center of the slope portions indicated by 1308 and 1309. As in the previous case, the position of the pulse signal when the rotational speed of the motor becomes equal to the target rotational speed is the position indicated by t5□. At this time, if the rotational speed of the motor is exactly equal to the target rotational speed, the pulse generation position after a certain time will be the position indicated by 0 at t54. Actually, the amount 13 of the phase error signal obtained at the position t52
10, the rotational speed is accelerated, and the pulse signal generation position after a certain time becomes the position indicated by t53.

At this time, the phase correction amount that moves after a certain time is 13
The 0 phase correction amount 1311, which is the amount indicated by 11, is (13b
) is larger than the phase correction amount 1306 shown in ). This is because the phase error amount shown by 1310 is larger than the phase error amount shown by 1302, so the rotation speed can be increased by that amount.The larger the 0 phase correction amount, the faster the time to reach the stable point. , the pull-in time can be shortened.

In order to minimize the pull-in time of the phase control system, use the phase error signal at that point to ensure that the pulse generation position of the next controlled signal occurs at a stable point, and to avoid overrun. For example, (13d)
Taking as an example the pull-in from position t52 shown in Figure 1, the next pulse generation position is the stable point of the proportional slope section, that is, 13
This is the position indicated by 09, and it is sufficient as long as there is no overrun.

In the present invention, when the pulse generation position of the controlled signal is at a position above and outside the proportional slope part when the rotational speed becomes approximately constant, the next pulse generation position is approximately at the center of the proportional slope part (stable point). The present invention provides a method for modulating the rotational speed, which is located at It should be noted that when the first pulse generation position of the controlled signal is on the proportional slope part, the pull-in may be performed by the response of the normal phase control system, and the pull-in time at this time is not so long as to cause a problem.

Next, it will be explained that changing the phase error amount is equivalent to changing the speed reference value.

FIG. 11 is a block diagram showing a part of the speed and phase control system, and FIG. 12 is an equivalent conversion of FIG. 11.

In FIG. 11, ω is a reference value of rotational speed, and specifically, it is given as a numerical value. ω is a value indicating the actual rotational speed of the rotating body, and specifically, the period of the FG signal is expressed numerically. ω.

and ω are manually generated with opposite polarity to each other, and the addition point is 110
5, the value of the difference between both speeds is taken.

Block 1101 is a block indicating speed comparison sensitivity, and a speed error signal 1108t- is obtained by multiplying the speed difference value by the speed comparison sensitivity.

θ1 is a phase reference value, and θ0 is a value indicating the rotational phase of the rotating body. The value of the difference between both phases taken out at the addition point 1106 is multiplied by the value of phase comparison sensitivity shown at 1102 to obtain a phase error signal 1109. Even if the phase difference with the reference signal is the same value, different phase error signals can be obtained by changing the value of the phase comparison sensitivity. That is, different values such as 1302 and 1310 shown in FIG. 13 can be set.

The speed error signal and the phase error signal are added at the addition point 110.
7, filter processing is performed at a filter block 1103, and output to a terminal 1104. Although not shown, the signal output to the terminal 1104 is D/A converted and then sent to a drive circuit for the rotating body to control the rotational speed and rotational phase of the rotating body.

FIG. 12 is a block diagram obtained by equivalently converting FIG. 11,
In the two diagrams, which are diagrams in which the phase error signal is converted into a form in which it is added to the reference value of the rotational speed, the same symbols represent the same elements. Such equivalent transformations are well known in control theory. Although a detailed explanation will be omitted, when changing the addition point of the phase error signal 1109 shown in FIG. The block 1204 shown in FIG. 12, which only needs to be multiplied by the signal, is
It is a transfer function with a value that is the reciprocal of speed comparison sensitivity.

In Fig. 12, the reference value ω of the rotational speed and the phase error signal 1
The actual rotational speed ω is subtracted from the sum of 205 and 205. In other words, the output signal 1206 of block 1201 is the reference value ω of the rotational speed shown in FIG.
, you can think about it! It becomes. From this, it can be said that changing the value of the phase error signal is equivalent to changing the reference value of the rotational speed.

Next, a method of modulating the rotational speed according to the present invention will be explained.

FIG. 2 is a diagram for explaining how a change in rotational speed affects the rotational phase. In the same figure (2
a) shows a signal phase-synchronized with the reference signal. (2bl)
, (2b 2), and (2b 3) are diagrams showing the rotational phase, rotational speed, and rotational position of the rotating body under the same conditions, respectively. (2cl), (2c2), (2c 3) are
It is a figure which shows the rotational phase, rotational speed, and rotational position of a rotating body under other same conditions. (2d) shows the time.

The pulse signal shown in (2bl) is a signal indicating the rotational phase of the rotating body. For example, a pulse signal is generated once per rotation of the rotating body, and its period is T.

When the rotational speed is approximately equal to the reference speed, ω, the pulse signal generation position is the position indicated by t2o, that is, the stable position of the phase control system. At this time, the next pulse generation position is at time t23, and the change in the 0 rotation position, which also becomes a stable position, can be obtained by integrating the rotation speed.The 0 rotation speed is ω. Ba,
The rotational position changes in a constant manner as shown by 203 in (2b3). The change θh1 in the rotational position at any given time can be expressed by the following equation, where t is a time variable.

θh1=ω. -t... (1) If the rotational position at time t2o is zero, the rotational position 204 at time t23 can be found by substituting one period T for time t in equation (1). If the amount of θh1 at this time matches the amount of one rotation of the rotating body, the pulse signal indicating the rotational phase can always maintain a constant phase relationship with the reference signal.

Next, assume that the pulse generation position when the rotational speed reaches a substantially constant speed ω is at time t21 as shown in (2cl). Then, at time t21, the rotation speed is changed to ω
Let us consider the change in the rotational position when the speed is changed to ω and then changed to the speed ω again at time t22. The change in rotational position at this time is shown in (2c 3), that is, ω until time t2□.

shows a change 205 in the rotational position according to ω1, and the darkness from time t21 to t22 shows a change 205 in the rotational position according to ω1,
After time t23, ω again. When the rotational position at time t12 indicating the change in rotational position according to is zero, time t2
The amount of change θh2 (indicated by 208) in the rotational position at No. 3 can be expressed by the following equation.

θh2”ω1°(t22-t21)+ωo°(t23-
t22)...(2) The value of θ5 shown in equation (1) when the time is T, and (2)
When θh2 shown in the equation is equal, the next pulse signal shown in (2cl) will be generated at the position of time t23. This is because the amount of change in rotational position from pulse signals 209 to 210 shown in (2bl) and the amount of change in rotational position from pulse signals 211 to 212 shown in (2cl) both correspond to one rotation of the rotating body. This is because they are quantities and are equal.

From the above, assuming θ (t=T)=θh2, (1)
By combining the equation and the equation (2), the equation (3) can be obtained.

Equation (3) is an equation that gives what value should be set for ω1. For example, the initial pulse signal generation time t
is T/2, and (t22-t2□)=(t-
t )=T/4, then ω1=3·ω. That is, in this case, the value of ω1 is set to 3 of the value of the reference speed ω.
All you have to do is double the setting.

The rotation speed at time t23 is ω. Therefore, the change in the rotational position after time t23 is the same as the change shown in (2b3). This shows that the pulse generation position after time t23 is always the stable position of the phase control system.
In other words, there will be no overrun.

As is clear from the above, depending on the position of the pulse signal when the rotational speed becomes approximately constant, (2c2)
If the rotational speed is changed as shown, the pulse generation position after one cycle will always be a stable position of the phase control system and will not cause overrun.

In FIG. 2, the explanation has been made assuming that the change in rotational speed occurs instantaneously. However, the actual change in rotational speed responds with a time delay. The influence of this time delay will be explained next.

Figure 3 shows various response waveforms with time delays. In FIG. 3A, the solid line in FIG. 3B, which shows a pulse signal indicating the rotational phase, shows the same change in rotational speed as shown in FIG. 2C2. The actual change in rotational speed has a time delay and has a response shown by a broken line 301.

The influence of the time delay at this time appears in the diagonally shaded areas 302 and 303. If the response of the control system is the same during acceleration and deceleration, the areas of 302 and 303 are equal. Therefore, whether the response is delayed or instantaneous, the amount of change in rotational position until the next pulse signal is generated is the same. That is, in this case, there is no need to consider time-delayed responses.

Figure (3q) is an example when the time for changing the rotational speed is increased. At this time, the rotation speed changes from ω2 to ω by the time the next pulse signal is generated.

Since the change has finished, there is no need to consider the influence of the transient period as explained in FIG. 3B, and the value of ω2 can be calculated using the above-mentioned equation (3).

Figure (3d) shows an example where the response of the speed control system is slow and an integral filter is built-in. The change in rotational speed at this time shows a nearly linear change as shown by the broken line. Then, the time for setting the rotational speed command to ω3 is the time t3 when the pulse signal is generated, and t3□
If the rotation speed is set to half the time difference T1 between
ω at 3°. Therefore, there will be no overrun.

Further, since the amount of change in the rotational position corresponds to the area indicated by the diagonal line 304, the value of this area may be set to be equal to the amount of change in the rotational position for one rotation.

Figure (3e) shows the rotational speed lI! : This is an example when the changing time is shorter than half of the time difference T1. At this time as well, the value of ω4 may be selected to be large so that no overrun occurs and the value of the area 305 is equal to the amount of change in the rotational position in one rotation.

Figure (3f) is an example in which the time for changing the rotational speed is longer than half of the time difference T1. At this time, the rotational speed is ω at time t32.

Therefore, the next pulse signal will not be generated at a stable position in the phase control system. In other words, it will overrun.

As is clear from the above explanation, when the rotation speed is changed to ω again after changing the rotation speed, if the change in the actual rotation speed is made to converge by the time when the next pulse signal is generated, then The rotational phase can be set to a stable state after one rotation, and overrun can be prevented. If the time for changing the rotational speed is set to be half or less than half of the time difference T1, overrun can be prevented regardless of the response time of the speed control system. Also, when the response time of the speed system is fast, the value for changing the rotational speed can be found using equation (3) above.On the other hand, when the response time of the speed system is slow, the details are omitted, but the speed change can be calculated by integrating the speed change. In addition, in a control system that has transient effects that cannot be obtained with a simple calculation formula, the optimum rotation can be determined by experiment. All you have to do is find the amount of change in speed. In any case, the rotational speed should be modulated according to the amount of rotational phase difference at a certain time, and the rotational speed should be converged to a steady state by the time the next pulse signal is generated, and overrun should not occur. is possible.

Next, specific embodiments of the present invention will be described.

FIG. 4 is a diagram showing one embodiment of the present invention, which is composed of a microcomputer (hereinafter simply referred to as microcomputer) section and other hardware circuits. FIG. 1 is a diagram to supplement the waveforms and explanation of each part in FIG. 4, and the same symbols in both figures indicate the same signals.

In FIG. 4, a terminal 401 receives an FC signal, a terminal 40
A reference signal (vertical synchronization signal in this example) is connected to terminal 40.
3 is a 0 circuit 404 to which the H and SW flaw signals are respectively input.
．． 405.406 are input capture registers (
Each ICR circuit (hereinafter simply referred to as ICR) is a latch circuit that latches the count value of the counter circuit 11407 at the rising or falling edge of each signal at the terminals 401 to 403. Counter circuit 407
is a free counter that counts the clock 408, and if the counter overflows, it starts counting again from the minimum value. The count value changes as shown in FIG. 1 (1d). In FIG. 1, the count value 101 at the falling edge of the H, SW flaw signal 1b)
is latched by a circuit 406 shown as ICR8 in FIG. Further, a count value 102 at the rising edge of a signal (IC) having a period of 1/2 of the reference signal is latched in a circuit 405 indicated by ICR2. Therefore, by subtracting the count value shown at 102 from the count value shown at 101, %10
If the constant phase reference value indicated by 3 is further subtracted, the amount indicated by the difference 104 will indicate the time corresponding to the amount of phase shift. A circuit 409 shown in FIG. 4 is a timer circuit, and H
, is reset at the falling edge of the SW flaw signal, and thereafter generates a pulse signal (1a) at regular intervals. As shown in FIG. 1, in this example, it is assumed that the time of the timer is set so that a pulse signal is generated every time when the H and SW signal period is divided into 1/12. 1ral shown in Figure 4
, l rq2.1 rq3 are pulse signals generated when each ICR circuit latches the value of the counter circuit, and are used as interrupt signals to the microcomputer. The output signal 1rq4 of the timer circuit 409 is similarly used as an interrupt signal. The 0 circuit 410 is a microcomputer, and the central processing unit 411, ROM 412, RAM 4
13 and an interrupt processing circuit 414.

As will be described later, the microcontroller calculates the speed error signal and the phase error signal using the values latched in each ICR circuit, synthesizes both signals, and then performs filter processing, and as a result, t'D/A It is supplied to the conversion circuit 415. The D/A converted output signal output to the terminal 416 is supplied to the motor drive circuit to control the rotation speed and rotation phase of the motor.

FIG. 1(1e) shows the phase error signal output.

The signal shown in (1e) consists of a proportional slope portion 107 and other portions 106 and 108. This signal is phase-synchronized with the H, SW flaw signal b). Since the phase reference value 103 is a constant value, the phase error signal when the rising edge of the signal (1c) is at the position shown in FIG. 1 is at the level shown at 105. The amount of phase error signal when the signal (1c) shifts to the left on the paper from the position shown in the diagram relative to the H and SW scratch signals is the amount of phase error signal that shifts to the left on the paper by the same amount from the position shown at 105. The value will be the value at the position. Signal (1
You can use the same idea when c) shifts to the right, 11
When the phase error signal at the position indicated by 9 is obtained, the signal (1
The rising edge of c) is at the time position indicated by t9 in FIG. 1(1a). Furthermore, when the phase error signal at the position indicated by 110 is obtained, the rising edge of the signal (1c) is
It is at the time position indicated by t7 in FIG. Therefore, the value of t (+=1.2.3,...) at the time when the rising edge of signal (1c) is input, that is, when the lrq2 interrupt shown in FIG. 4 occurs, is If you are selfish,
It is possible to know whether the phase error region is in 106, 107, or 108. When the phase difference between the rotational phase of the rotating body and the reference signal is in the region of the proportional slope section 107, it can be determined in 104. The value shown is output as a phase error signal in the area where the 0 phase shift is outside the proportional slope area, 106 and 1.
Each level of the 0 staircase wave signal, for example, 111 and 112, outputs a phase error signal corresponding to the level of the staircase wave signal as shown in the same figure when it is located at 08, and the level of the 0 staircase wave signal, for example, 111 and 112, is changed at each timer interrupt indicated by 1rq4. As explained above, each level of the 0 staircase wave signal to which is selected so that it occurs near the central position of

FIG. 5 is a diagram showing the procedure of signal processing performed by the microcomputer. In the figure, FG(k) indicates the count value latched in I CRI at the time of the second FG flaw signal, for example, the rising edge. FG(k-1) is (k
-1)th FG flaw signal rising edge time, that is, a value latched one cycle before FG(k). The value 501 of the difference between the values of FC(k) and FC(k-1'l) corresponds to the FG flaw signal period.This value 50
A value 502 obtained by taking the difference between 1 and the speed reference value is a speed error signal.

On the other hand, as a process to obtain a phase error signal, the count value latched at the falling edge of the H, SW multiplied signal shown at 503 and the signal (1/2 period) of the reference signal shown at 504 are used.
A phase error signal 506 is obtained by calculating the difference 505 from the count value latched at the rising edge of 2 V, NC) and subtracting the phase reference value from this value 505. The mix ratio setting process 507 is a process for setting a mix ratio when combining the speed error signal 502 and the phase error signal 506, and is a process for determining the amount of phase error output shown in FIG. 1(1e). The specific process of setting the mix ratio is performed by the process of the interrupt Irq3 generated by the falling edge of the H-SW double signal.

The composite signal 508 of the speed error signal and the phase error signal is processed by digital filter processing 5 such as a proportional integral filter.
After passing through step 09, the signal is output to the D/A conversion circuit in step 510.

Next, a specific processing procedure by the microcomputer for realizing the signal processing explained using FIG. 5 will be explained using FIGS. 6 to 10.

Figure 6 shows the electricity! It is a flowchart which shows the routine of the main process started after input. In the figure, process 601 is an initial value setting process that performs processes such as setting the values of each RAM to zero.

In process 602, it is determined whether the level of the H0SW signal is H1gh level or not. If it is not H1gh level, a time wait is performed, and if it is H1gh level, process 1 shown in 603 is performed.
Execute. In addition, in process 604, it is determined whether the H-SW double signal level is Low level or not, and if it is not Low level, a time wait is performed, and if it is Low level, 60
Processing 2 shown in 5 is executed. After executing process 2, process 602 is executed again. Process 1 indicated by 603 and 605
Processing 2 is, for example, a process of decoding serial data transmitted from the system control circuit and determining the current mode, etc., but since it is not directly related to the present invention, a detailed explanation thereof will be omitted. is omitted. While executing the main processing routine shown in FIG. 6, if each of the interrupt signals 1rq1 to 1rq4 described in FIG. 4 is generated, each side-in processing is performed as appropriate.

In addition, in each subsequent process, the symbol enclosed in () represents each R.
0 indicating the name of AM For example, the meaning of (FGN) is (F
(GN) means FLAM, but in the following explanation, (FGN) has the same meaning.

FIG. 7 shows a process executed when an interrupt of 1 rql occurs, and is a process for obtaining a speed error signal. In the figure, process 701 is a process of transferring the count value of the counter circuit 407 at the time when the 1rql interrupt occurs to (FGN). In process 702, the count value stored in (FGO) when the 1rql interrupt signal was generated one period before the FG multiplication signal is subtracted from the count value of (FGN), and the result is stored in (WKl).

In process 703, a value obtained by subtracting the speed reference value from the value of (WKI), that is, a speed error signal, is stored in (S P D). Through this process, the value shown in FIG. 5 502 is stored in (SPD).

Processing 704 converts the current count value stored in (FGN) to (FGN) in preparation for calculation at the time of the next 1rq1 interrupt.
GO). The value of this (FGO) is
It is used in process 702 when the next Irql interrupt occurs.

Each process shown in FIG. 8 is a process executed when an interrupt of Irq2 occurs. In the figure, processing 80
1 is a process of increasing (CTV) by the value t-1.

(CTV) is a RAM required to divide the input reference signal into 1/2. In process 802, (CT V
) is smaller than 2, and if it is smaller, it is set to 1.
Finish processing rq2. If larger, process 803.804
is executed, the value of (CT V) is set to zero in process 805, and the process of 1rq2 is completed. By performing such processing, processing 803, 804 and 805
It is executed once every two interrupts. In other words, this is the same as dividing the reference signal into 1/2. Processing 803 is executed every cycle in which the reference signal is divided into 1/2, and the count value of the counter circuit 407 at this time is stored in (VS). This value of (VS) corresponds to the value 504 explained in FIG. Processing 804 is (
This process stores the value of (CTT) in (PTV).

(CTT) includes 1, (+=1.
2.3,...) is stored. Therefore, depending on the value of (P T V), as shown in Fig. 1 (1e)
In order to obtain the phase error signal shown in , it is sufficient to perform a process of varying the mix ratio of the phase error signal to be combined with the speed error signal, and this process is performed in the process of 1rq3.

Each process shown in FIG. 9 is a process executed when an i rq3 interrupt occurs, and in process 901, which represents the main process for realizing the present invention, the value of (CTT) is set to 1.
Set to . That is, the process resets the value of t shown in FIG. 1 (1a) to tl at the timing of the falling edge of the H, SW signal (1b). Process 902 is a process for storing the output value of the counter circuit 407 at this time in (H5). Processing 903 is performed from the value of (H5) in FIG.
Subtract the value of (VS) explained in the process of 03, and (WK2
'). In process 904, (WK2
) The value obtained by subtracting the phase reference value from the value is stored in (PHE). Through these processes, (P) and (E) are shown in Fig. 5.
The value of the phase error signal indicated by 06 is stored. Processing 90
5 is the value of the mix ratio according to the value of (PTV) ft0
A value for weighting the phase error signal 506, that is, a mix ratio value, is written in the ROM table that performs the process of reading from the M table in order to obtain the phase error output shown in FIG. 1 (1e). . This value is (P T V
) and performs the next process 906. Process 906 divides the phase error signal (PHE) by the mix ratio and stores it again in (PHE), and calculates the actual phase to be combined with the speed error signal. This is the process of creating an error signal. Note that the process 906 shows the process of dividing the phase error signal (PHE) by the mix ratio, but depending on the numerical value handled, (PHE
It goes without saying that the value of E) may be multiplied by the mix ratio. By performing the above processing, it is possible to create a phase error signal weighted according to the amount of phase error.

Each process shown in FIG. 10 is a process executed when an interrupt of irq4 occurs. In this process, the value of 1 indicated by t is incremented by 1. Processing 1002 is a process of synthesizing the (SPD) i7) value obtained in the processing 703 of 1 rql and the value of (PHE) obtained in the processing of l rq3, that is, the speed error signal (SPD) and the phase error signal ( This process combines each part with (PHE) and stores the combined value in (SPD). Processing 1003 is a process of performing calculations for a filter unit necessary for the control system, but since this calculation is not the main purpose of the present invention, detailed explanation will be omitted. Processing 1004 is a process of combining the speed error signal and the phase error signal and outputting the synthesized signal to the D/A conversion circuit.

The above is a description of specific embodiments of the present invention.

In addition, in the explanation so far, we have explained a method of changing the output of the phase error signal as a method of modulating the rotation speed, but the same effect can be obtained even if the reference value of the rotation speed is changed and the rotation speed is modulated. It will be clear from the explanation in FIGS. 11 and 12 that the following can be obtained.

In addition, during the period from when the speed of the rotating body becomes approximately constant until the phase control system becomes stable, the response frequency of the speed control system is set higher than the response frequency during steady state, as shown in Figure 3 (
It is possible to perform a fast response as shown in 3b).

Furthermore, in the explanation so far, the period of the pulse signal indicating the rotational phase has been explained as being equivalent to one rotation of the rotating body, but the pulse signal indicating the rotational phase is a pulse signal that occurs multiple times in one rotation. It goes without saying that similar effects can be expected by using .

In addition, in the description of the present invention, the control method after the rotation speed reaches a substantially constant value has been explained in detail, but the phase error signal output until the rotation speed reaches a constant value is, for example, It may be fixed to a value equal to the phase error signal output value in a stable state.

Effects of the Invention As is clear from the above explanation, according to the present invention, by modulating the rotational speed according to the generation position of a pulse signal indicating the rotational phase when the rotational speed becomes approximately constant,
The generation position of the pulse signal indicating the next rotational phase can be set to the pulse signal generation position where the phase control system is in a stable state, and overrun can be prevented. That is, the pull-in time of the phase control system can be shortened to a time corresponding to one cycle of the pulse signal indicating the rotational phase.

[Brief explanation of the drawing]

Fig. 1 is a signal waveform diagram in one embodiment of the present invention, Fig. 2 is an explanatory diagram showing the concept of the rotation speed modulation method according to the present invention, and Fig. 3 is an actual rotation speed when implementing the present invention. 4 is a block diagram showing an embodiment of the present invention. FIG. 5 is an explanatory diagram showing the flow of signals in a specific embodiment of the present invention. FIG. 6 is a main processing routine. Flowchart, FIG. 7 is a flowchart for obtaining a speed error signal, FIG. 8 is a flowchart showing a processing procedure for holding a count value at 1/2 period of the reference signal, and FIG. 9 is a processing procedure for obtaining a phase error signal. A flowchart showing
FIG. 10 is a flowchart showing each process executed during timer interrupt processing, FIG. 11 is a block diagram of the part that mixes the speed error signal and phase error signal, FIG. 12 is a block diagram that is a modification of FIG. 11, Figure 13 is an explanatory diagram showing the concept of the pull-in time of the phase control system, and Figure 14 is an explanatory diagram showing the concept of the pull-in time of the phase control system.
FIG. 6 is a waveform diagram showing waveforms of various parts of the conventional phase comparator circuit, FIG. 15 is a system diagram of the conventional speed and phase control circuit, and FIG. 16 is a block diagram of the conventional phase comparator circuit. 404-406...input capture register,
414...Interrupt processing circuit, SPD...RAM for storing the value of speed error signal, CTT...RAM for storing the number of timer interrupts, PTV...Reference signal is 1
RAM that stores the value of the timer interrupt at the time of manual input every /2 cycle, PHE...FtAM that stores the value of the phase error signal. Name of agent Patent attorney Toshio Nakao 1 person Figure 1 Figure 2 Figure 3 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 L J Figure 13 Figure 14

Claims (2)

[Claims] (1) A control circuit that obtains a speed error signal and a phase error signal as digital signals and drives a controlled object with a signal obtained by combining the speed error signal and the phase error signal, comprising a modulation means for modulating the rotation speed, The modulating means is configured such that when the phase difference between the phase reference signal and the controlled signal is within a certain phase error range, the amount of the phase error signal changes in proportion to the phase difference, and is outside a certain phase range, during the period between the current phase comparison timing t_p of the controlled signal and the time t_n of the next controlled signal phase comparison timing, the rotational speed is accelerated or faster than the rotational speed at time t_p. A period of driving at a reduced rotational speed and a period of maintaining the rotational speed at steady state are provided, and the amount of change in the rotational phase in the time from t_p to t_n is equal to the rotation of the controlled signal during steady rotation. A phase control circuit characterized in that the acceleration or deceleration level is set to correspond to one phase period. (2) A patent claim characterized in that the time for acceleration or deceleration from t_p to t_n is set to 1/2 of the time from t_p to t_n or less. The phase control circuit according to range 1.