JPS6011809B2 - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPS6011809B2 JPS6011809B2 JP55169868A JP16986880A JPS6011809B2 JP S6011809 B2 JPS6011809 B2 JP S6011809B2 JP 55169868 A JP55169868 A JP 55169868A JP 16986880 A JP16986880 A JP 16986880A JP S6011809 B2 JPS6011809 B2 JP S6011809B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- substrates
- insulating film
- conductive path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
【発明の詳細な説明】 本発明は混成集積回路の改良に関する。[Detailed description of the invention] The present invention relates to improvements in hybrid integrated circuits.
従来の混成集積回路は第１図に示す如く、金属基板１の
一主面に絶縁薄層を設けて所望の導電略２を設け、導電
路２上に半導体集積回路、チップ抵抗あるいはチップコ
ンデンサー等の回路素子３を固着して、第２図の如く外
部リード４のみを残して全体を樹脂５でモールドして形
成していた。As shown in FIG. 1, a conventional hybrid integrated circuit has a thin insulating layer provided on one main surface of a metal substrate 1 to provide desired electrical conductivity 2, and a semiconductor integrated circuit, chip resistor, chip capacitor, etc. on the conductive path 2. The circuit element 3 was fixed, and the whole was molded with resin 5, leaving only the external leads 4, as shown in FIG.
斯る混成集積回略は金属基板１の一主面に形成されるた
め、ある程度の集積度を確保するには高さが必要となり
、鰭子機器の薄型化設計の難点となっていた。この原因
は主として外部リード４の固着パッド６にかなりの面積
が必要となるためである。本発明は斯点に鑑みてなされ
、従来の欠点を除去した混成集積回路を提供するもので
あり、以下に第３図乃至第５図を参照して本発明の一実
施例を詳述する。Since such a hybrid integrated circuit is formed on one main surface of the metal substrate 1, a height is required to ensure a certain degree of integration, which has been a difficulty in designing thinner fin devices. This is mainly due to the fact that the fixing pad 6 of the external lead 4 requires a considerable area. The present invention has been made in view of this point and provides a hybrid integrated circuit that eliminates the conventional drawbacks.One embodiment of the present invention will be described in detail below with reference to FIGS. 3 to 5.
本発明の混成集積回路は第３図および第４図に示す如く
、２枚の金属基板１１，１２と、基板１１，１２を接続
する絶縁フィルム１３と、フィルム１３上に設けた導電
路１４と、導蟹路１４上に固着した半導体集積回路、チ
ップ抵抗あるいはチップコンデンサー等の複数の回路素
子１５とを具備している。As shown in FIGS. 3 and 4, the hybrid integrated circuit of the present invention includes two metal substrates 11 and 12, an insulating film 13 connecting the substrates 11 and 12, and a conductive path 14 provided on the film 13. , and a plurality of circuit elements 15 such as a semiconductor integrated circuit, a chip resistor, or a chip capacitor fixed on the guide path 14.
金属基板１１，１２は０．５〜１．０脚厚の良熱伝導性
のアルミニウムで形成され、ェポキシ樹脂等の接着剤に
より基板１１，１２を夫々の厚みだけ離間させてポリィ
シド等の絶縁フィルム１３で接続する。The metal substrates 11 and 12 are made of aluminum with good thermal conductivity and have a thickness of 0.5 to 1.0 mm.The substrates 11 and 12 are separated by their respective thicknesses using an adhesive such as epoxy resin, and then an insulating film such as polycid is used. Connect with 13.
絶縁フィルム１３の反対主面には導電路１４となる鋼箔
を貼着しておき、鋼箔を選択的にエッチングして所望形
状の導電磁１４を形成する。導電路１４は第３図からも
明らかな様に一方の基板１２の端部に外部リード１６を
半田付けするパッド１７を並べ、パッド１７から導電路
１４を絶縁フィルム１３上に延在させる。回路素子１５
を固着する導電路１４の部分は両方の基板１１．１２上
に位鷹する様に設計し、基板１１，１２の離間部分には
折り曲げのため回路素子１５を設けなし、。回路素子１
５を組込んだ後、基板１１．１２の離間部分で絶縁フィ
ルム１３を折り曲げて第５図に示す如く、基板１１．１
２の夫々の反対主面をちようど当俵させて、外部リード
１６を残して全体を樹脂１８でモードルする。A steel foil serving as a conductive path 14 is pasted on the opposite principal surface of the insulating film 13, and the conductive electromagnetic field 14 of a desired shape is formed by selectively etching the steel foil. As is clear from FIG. 3, pads 17 to which external leads 16 are soldered are arranged at the end of one substrate 12, and the conductive path 14 extends from the pads 17 onto the insulating film 13. Circuit element 15
The portion of the conductive path 14 that fixes the circuit is designed to be placed on both substrates 11 and 12, and the circuit element 15 is not provided in the separated portion of the substrates 11 and 12 due to bending. circuit element 1
5, the insulating film 13 is bent at the separated part of the substrate 11.12, and the substrate 11.1 is assembled as shown in FIG.
The opposite main surfaces of each of the parts 2 and 2 are then placed in place, and the entire body is molded with resin 18, leaving the external leads 16.
本発明に依れば、従釆と同じ集積度を有する混成集積回
路を約半分の高さにでき「且つフレキシブルな絶縁フィ
ルム１３を採用することによって両基板１１，１２の導
電路１４の接続も不要となり従釆と同様の方法で製造で
きる。According to the present invention, it is possible to reduce the height of a hybrid integrated circuit having the same degree of integration as that of the secondary circuit by about half, and by employing the flexible insulating film 13, the conductive paths 14 of both substrates 11 and 12 can be connected. It is no longer needed and can be manufactured using the same method as the subordinate.
この結果従釆では基板の片面利用であったものが、本発
明では基板の両面利用と等価となり混成集積回路の４・
型化に大きく寄与できる。As a result, in the conventional system, one side of the board was used, but in the present invention, it is equivalent to the use of both sides of the board, and the four parts of the hybrid integrated circuit.
It can greatly contribute to molding.
第１図は従来の混成集積回路を説明する平面図、第２図
はその側面断面図、第３図は本発明による混成集積回路
を説明する平面図、第４図はその側面断面図、第５図は
本発明の完成した混成集積回路の断面図である。
１１，１１２は金属基板、１３は絶縁フィルム、１４は
導電路、１５は回路素子、１６は外部ＩＪ−ド、１７は
パッド、１８は樹脂である。
第１図
第２図
第３図
第４図
第５図1 is a plan view illustrating a conventional hybrid integrated circuit, FIG. 2 is a side sectional view thereof, FIG. 3 is a plan view illustrating a hybrid integrated circuit according to the present invention, and FIG. 4 is a side sectional view thereof. FIG. 5 is a sectional view of the completed hybrid integrated circuit of the present invention. 11 and 112 are metal substrates, 13 is an insulating film, 14 is a conductive path, 15 is a circuit element, 16 is an external IJ-doard, 17 is a pad, and 18 is a resin. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
縁フイルムと該フイルム上に設けた所望形状の導電路と
該導電路上に固着される複数の回路素子とを具備し、両
基板間の前記絶縁フイルムを曲折して前記基板の反対主
面を接する様に配置し、前記両基板に設けた回路素子を
前記絶縁フイルムの曲折部分上に延在される導電路を介
して接続することを特徴とする混成集積回路。1 Comprising two metal substrates, an insulating film that connects the metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements fixed on the conductive path, and between the two substrates. The insulating film is bent and arranged so that the opposite main surfaces of the substrate are in contact with each other, and the circuit elements provided on both the substrates are connected via a conductive path extending on the bent portion of the insulating film. A hybrid integrated circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55169868A JPS6011809B2 (en) | 1980-12-01 | 1980-12-01 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55169868A JPS6011809B2 (en) | 1980-12-01 | 1980-12-01 | hybrid integrated circuit |
Related Child Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61193474A Division JPS62149145A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
| JP19347686A Division JPS62115761A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
| JP61193477A Division JPS62149147A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
| JP61193475A Division JPS62149146A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
| JP19347386A Division JPS62149144A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5792852A JPS5792852A (en) | 1982-06-09 |
| JPS6011809B2 true JPS6011809B2 (en) | 1985-03-28 |
Family
ID=15894430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55169868A Expired JPS6011809B2 (en) | 1980-12-01 | 1980-12-01 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6011809B2 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6287449U (en) * | 1985-11-20 | 1987-06-04 | ||
| JPS6287450U (en) * | 1985-11-20 | 1987-06-04 | ||
| JPS62116544U (en) * | 1986-01-13 | 1987-07-24 | ||
| JPS62118439U (en) * | 1986-01-17 | 1987-07-28 | ||
| JPS62252954A (en) * | 1986-04-25 | 1987-11-04 | Mitsubishi Electric Corp | Semiconductor device |
| JPS62115761A (en) * | 1986-08-18 | 1987-05-27 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| JPS62149147A (en) * | 1986-08-18 | 1987-07-03 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| JPS62149146A (en) * | 1986-08-18 | 1987-07-03 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| JPS62149145A (en) * | 1986-08-18 | 1987-07-03 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| JPS62149144A (en) * | 1986-08-18 | 1987-07-03 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
| JPS63180965U (en) * | 1987-05-13 | 1988-11-22 | ||
| JPH02290093A (en) * | 1990-04-25 | 1990-11-29 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
-
1980
- 1980-12-01 JP JP55169868A patent/JPS6011809B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5792852A (en) | 1982-06-09 |
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