JPS62118439U - - Google Patents
Info
- Publication number
- JPS62118439U JPS62118439U JP532286U JP532286U JPS62118439U JP S62118439 U JPS62118439 U JP S62118439U JP 532286 U JP532286 U JP 532286U JP 532286 U JP532286 U JP 532286U JP S62118439 U JPS62118439 U JP S62118439U
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- conductive path
- metal substrates
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示す平面図、第２図
および第３図は従来例を示す断面図および平面図
である。
１，２…金属基板、３…絶縁フイルム、４…導
電路、５…回路素子、６…外部リード。
FIG. 1 is a plan view showing an embodiment of the present invention, and FIGS. 2 and 3 are a sectional view and a plan view showing a conventional example. DESCRIPTION OF SYMBOLS 1, 2... Metal substrate, 3... Insulating film, 4... Conductive path, 5... Circuit element, 6... External lead.
Claims (1)
て結合する絶縁フイルムと、該フイルム上に設け
た所望形状の導電路と、該導電路上に固着される
複数の回路素子とを具備し、前記絶縁フイルムを
曲折して前記二枚の金属基板の金属露出面を接す
る様に配置した混成集積回路に於いて、前記絶縁
フイルムの折曲げ部分にある導電路の曲折部のコ
ーナー部を面取りすることを特徴とする混成集積
回路。 It includes two metal substrates, an insulating film that connects the two metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements fixed on the conductive path. In a hybrid integrated circuit in which the insulating film is bent so that the exposed metal surfaces of the two metal substrates are in contact with each other, the corner portion of the bent portion of the conductive path at the bent portion of the insulating film is A hybrid integrated circuit characterized by chamfering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP532286U JPS62118439U (en) | 1986-01-17 | 1986-01-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP532286U JPS62118439U (en) | 1986-01-17 | 1986-01-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62118439U true JPS62118439U (en) | 1987-07-28 |
Family
ID=30786797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP532286U Pending JPS62118439U (en) | 1986-01-17 | 1986-01-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62118439U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184384A (en) * | 1989-12-13 | 1991-08-12 | Nec Corp | Optical module submount and manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
-
1986
- 1986-01-17 JP JP532286U patent/JPS62118439U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184384A (en) * | 1989-12-13 | 1991-08-12 | Nec Corp | Optical module submount and manufacture thereof |