JPS62116544U - - Google Patents
Info
- Publication number
- JPS62116544U JPS62116544U JP275286U JP275286U JPS62116544U JP S62116544 U JPS62116544 U JP S62116544U JP 275286 U JP275286 U JP 275286U JP 275286 U JP275286 U JP 275286U JP S62116544 U JPS62116544 U JP S62116544U
- Authority
- JP
- Japan
- Prior art keywords
- metal substrates
- insulating film
- conductive path
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示す断面図、第２図
は従来例を示す断面図である。
１，２……金属基板、３……絶縁フイルム、４
……導電路、５……回路素子、６……外部リード
、７……接着シート。
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional example. 1, 2... Metal substrate, 3... Insulating film, 4
... Conductive path, 5 ... Circuit element, 6 ... External lead, 7 ... Adhesive sheet.
Claims (1)
て結合する絶縁フイルムと、該フイルム上に設け
た所望形状の導電路と、該導電路上に固着される
複数の回路素子とを具備し、前記絶縁フイルムを
曲折して前記二枚の金属基板の金属露出面を接す
る様に配置した混成集積回路に於いて、前記二枚
の金属露出面を接着シートで固着することを特徴
とした混成集積回路。 It includes two metal substrates, an insulating film that connects the two metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements fixed on the conductive path. In the hybrid integrated circuit in which the insulating film is bent so that the exposed metal surfaces of the two metal substrates are in contact with each other, the exposed metal surfaces of the two metal substrates are fixed with an adhesive sheet. Hybrid integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP275286U JPS62116544U (en) | 1986-01-13 | 1986-01-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP275286U JPS62116544U (en) | 1986-01-13 | 1986-01-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62116544U true JPS62116544U (en) | 1987-07-24 |
Family
ID=30781888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP275286U Pending JPS62116544U (en) | 1986-01-13 | 1986-01-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62116544U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
-
1986
- 1986-01-13 JP JP275286U patent/JPS62116544U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |