JPS63114039U - - Google Patents
Info
- Publication number
- JPS63114039U JPS63114039U JP570687U JP570687U JPS63114039U JP S63114039 U JPS63114039 U JP S63114039U JP 570687 U JP570687 U JP 570687U JP 570687 U JP570687 U JP 570687U JP S63114039 U JPS63114039 U JP S63114039U
- Authority
- JP
- Japan
- Prior art keywords
- metal substrates
- insulating film
- conductive path
- circuit elements
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
第１図は本考案の実施例を示す断面図であり第
２図の―断面図、第２図は本実施例の側面図
、第３図は第２図の平面図、第４図乃至第７図は
従来例を示す図である。
１……金属基板、２……絶縁フイルム、３……
枠体、４……導電路、５……回路素子、６……外
部リード、７……蓋体、８……封止空間、９……
リード空間、１０……突出部、１０′……切り欠
き部。
1 is a cross-sectional view showing an embodiment of the present invention; FIG. 2 is a cross-sectional view of FIG. 2; FIG. FIG. 7 is a diagram showing a conventional example. 1... Metal substrate, 2... Insulating film, 3...
Frame, 4... Conductive path, 5... Circuit element, 6... External lead, 7... Lid, 8... Sealed space, 9...
Lead space, 10...projection, 10'...notch.
Claims (1)
して結合する絶縁フイルムと、前記フイルム上に
設けた所望形状の導電路と、前記導電路上に固着
される複数の回路素子とを具備し、前記金属基板
間の絶縁フイルムを折曲し前記回路素子が対向す
る様に配置し且つ前記金属基板を一定間隔離間配
置する枠体と、前記金属基板の終端側面に固着す
る蓋体とを備えたことを特徴とする混成集積回路
。 It includes two metal substrates, an insulating film that connects the two metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements fixed on the conductive path. and a frame body in which the insulating film between the metal substrates is bent so that the circuit elements face each other and the metal substrates are spaced apart for a certain period of time, and a lid body fixed to a terminal side surface of the metal substrate. A hybrid integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP570687U JPH06824Y2 (en) | 1987-01-19 | 1987-01-19 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP570687U JPH06824Y2 (en) | 1987-01-19 | 1987-01-19 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63114039U true JPS63114039U (en) | 1988-07-22 |
| JPH06824Y2 JPH06824Y2 (en) | 1994-01-05 |
Family
ID=30787542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP570687U Expired - Lifetime JPH06824Y2 (en) | 1987-01-19 | 1987-01-19 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06824Y2 (en) |
-
1987
- 1987-01-19 JP JP570687U patent/JPH06824Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06824Y2 (en) | 1994-01-05 |
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