JPS6398647U - - Google Patents

Info

Publication number
JPS6398647U
JPS6398647U JP19476086U JP19476086U JPS6398647U JP S6398647 U JPS6398647 U JP S6398647U JP 19476086 U JP19476086 U JP 19476086U JP 19476086 U JP19476086 U JP 19476086U JP S6398647 U JPS6398647 U JP S6398647U
Authority
JP
Japan
Prior art keywords
metal substrates
insulating film
conductive path
circuit elements
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19476086U
Other languages
Japanese (ja)
Other versions
JPH0442937Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19476086U priority Critical patent/JPH0442937Y2/ja
Publication of JPS6398647U publication Critical patent/JPS6398647U/ja
Application granted granted Critical
Publication of JPH0442937Y2 publication Critical patent/JPH0442937Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す斜視図、第2図
は第1図の―断面図、第3図乃至第6図は従
来例を示す図である。 1……金属基板、2……絶縁フイルム、3……
ケース、6……外部リード。
FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view along the line shown in FIG. 1, and FIGS. 3 to 6 are views showing conventional examples. 1... Metal substrate, 2... Insulating film, 3...
Case 6...External lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 二枚の金属基板と、前記金属基板を離間して結
合する絶縁フイルムと、前記フイルム上に設けた
所望形状の導電路と、前記導電路上に固着される
少なくとも発熱を有する複数の回路素子とを具備
し、前記金属基板間の絶縁フイルムを折曲し前記
回路素子が対向する様に配置し、前記二枚の金属
基板を離間固着するコ字状のケース材を前記二枚
の金属基板の周端部に配して一体化することを特
徴とする混成集積回路。
Two metal substrates, an insulating film that connects the metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements that generate at least heat and are fixed on the conductive path. The insulating film between the metal substrates is bent so that the circuit elements face each other, and a U-shaped case material for separating and fixing the two metal substrates is placed around the two metal substrates. A hybrid integrated circuit characterized by being arranged and integrated at the end.
JP19476086U 1986-12-18 1986-12-18 Expired JPH0442937Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19476086U JPH0442937Y2 (en) 1986-12-18 1986-12-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19476086U JPH0442937Y2 (en) 1986-12-18 1986-12-18

Publications (2)

Publication Number Publication Date
JPS6398647U true JPS6398647U (en) 1988-06-25
JPH0442937Y2 JPH0442937Y2 (en) 1992-10-12

Family

ID=31152030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19476086U Expired JPH0442937Y2 (en) 1986-12-18 1986-12-18

Country Status (1)

Country Link
JP (1) JPH0442937Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012151173A (en) * 2011-01-17 2012-08-09 Nec Corp Three-dimentional mounting type semiconductor device, and electronic apparatus
JP2016219715A (en) * 2015-05-26 2016-12-22 住友ベークライト株式会社 Insulation gate bipolar transistor element, resin composition, and surge countermeasure member

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012151173A (en) * 2011-01-17 2012-08-09 Nec Corp Three-dimentional mounting type semiconductor device, and electronic apparatus
JP2016219715A (en) * 2015-05-26 2016-12-22 住友ベークライト株式会社 Insulation gate bipolar transistor element, resin composition, and surge countermeasure member

Also Published As

Publication number Publication date
JPH0442937Y2 (en) 1992-10-12

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