JPH02290093A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH02290093A JPH02290093A JP2109111A JP10911190A JPH02290093A JP H02290093 A JPH02290093 A JP H02290093A JP 2109111 A JP2109111 A JP 2109111A JP 10911190 A JP10911190 A JP 10911190A JP H02290093 A JPH02290093 A JP H02290093A
- Authority
- JP
- Japan
- Prior art keywords
- boards
- insulating film
- pads
- substrates
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 45
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000011347 resin Substances 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 239000011889 copper foil Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
Landscapes
- Coupling Device And Connection With Printed Circuit (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Multi-Conductor Connections (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は混成集積回路に関し、特に折曲げ構造の混成集
積回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to improvements in a hybrid integrated circuit having a folded structure.
（口）従来の技術
従来の混成集積回路は第４図に示す如く、金属基板（１
〉の一主面に絶縁薄層を設けて所望の導電路（２）を設
け、導電路（２）上に半導体集積回路、チップ抵抗ある
いはチップコンデンサー等の回路素子＜３〉を固着して
、第５図の如く外部リード（４）のみを残して全体を樹
脂ク５）でモールドして形成していた。(Expression) Conventional technology A conventional hybrid integrated circuit has a metal substrate (one
〉 A thin insulating layer is provided on one main surface to provide a desired conductive path (2), and a circuit element <3> such as a semiconductor integrated circuit, a chip resistor or a chip capacitor is fixed on the conductive path (2), As shown in FIG. 5, the entire structure was formed by molding with resin (5), leaving only the external leads (4).
（ハ）発明が解決しようとする課題
斯る混成集積回路は金属基板（１）の一生面に形成され
るため、ある程度の集積度を確保するには高さが必要と
なり、電子機器の薄型化設計の備点となっていた。この
原因は主として外部リード（４）の固着パッド（６）に
かなりの面積が必要となるためである。(c) Problems to be solved by the invention Since such hybrid integrated circuits are formed on the entire surface of the metal substrate (1), a certain height is required to ensure a certain degree of integration, which leads to thinner electronic devices. This was a design consideration. This is mainly due to the fact that the fixing pad (6) of the external lead (4) requires a considerable area.
（二）課題を解決するための手段
本発明は上述した点に鑑みてなされたものであり、第１
図乃至第３図に示す如く、離間した二枚の金属基板（１
１）（１２）を絶縁フィルム（１３）で結合させ、絶縁
フィルム（１３）上に所望形状の導電路（１４）を設け
、導電路ク１４〉が延在される一方の金属基板ク１２）
の端部にバッド（１７）を設け、他方の金属基板（１２
）上のみにチップ状の集積回路素子あるいは能動素子の
回路素子ク１５）を搭載し、基板（１１）＜１２＞間の
絶縁フイルム（１３）を折曲げ基板（１１）（１２）の
反対主面を接する様に配置して解決する。(2) Means for Solving the Problems The present invention has been made in view of the above-mentioned points.
As shown in Figures to Figure 3, two metal substrates (1
1) (12) are combined with an insulating film (13), a conductive path (14) of a desired shape is provided on the insulating film (13), and one metal substrate (12) on which the conductive path (14) extends
A pad (17) is provided at the end of the other metal substrate (12).
) A chip-shaped integrated circuit element or an active circuit element 15) is mounted only on the top of the substrate (11) and the insulating film (13) between the substrates (11) and (12) are bent. Solve by arranging the surfaces so that they touch.
（ホ〉作用
斯上の如く、離間した二枚の金属基板を絶縁フィルｌ１
で結合し、絶縁フィルム上に設けるパッドを一方の金属
基板のみに設け、他方の金属基板上にチップ状の集積回
路素子あるいは能動素子の回路素子を搭載して夫の基板
の反対主面が接する様に基板間の絶縁フィルムを折曲げ
ることにより、一方の金属基板のみにリード固着パッド
が設けられているため同一面積においても他方の金属基
板の方がパッドを設けないので集積度が向上する。また
、基板を折曲げ配置するので混成集積回路の高さが半分
になる。(E) Operation As above, the two metal substrates separated by the insulation film l1
A pad on an insulating film is provided on only one metal substrate, and a chip-shaped integrated circuit element or an active element is mounted on the other metal substrate, and the opposite main surface of the other substrate is in contact with the other metal substrate. By bending the insulating film between the substrates in this way, lead fixing pads are provided on only one metal substrate, so even if the area is the same, the other metal substrate does not have any pads, so the degree of integration is improved. Furthermore, since the substrate is arranged in a bent manner, the height of the hybrid integrated circuit is halved.
（へ）実施例
以下に第１図乃至第３図に示した実施例に基づいて本発
明を詳述する。(f) Examples The present invention will be described in detail below based on the examples shown in FIGS. 1 to 3.
本発明の混成集積回路は第１図および第２図に示す如く
、二枚の金属基板＜１１＞（１２）と、基板（１１）（
１２）を接続する絶縁フィルム（１３）と、フィルム（
１３）上に設けた導電路（１４）と、導電路（１４）上
に固着した半導体集積回路、能動素子、チップ抵抗ある
いはチップコンデンザー等の複数の回路素子ク１５）と
を具備している。As shown in FIGS. 1 and 2, the hybrid integrated circuit of the present invention includes two metal substrates <11> (12) and a substrate (11) (
12) and an insulating film (13) that connects the film (
13) A conductive path (14) provided on the conductive path (14) and a plurality of circuit elements 15) such as semiconductor integrated circuits, active elements, chip resistors, or chip capacitors fixed on the conductive path (14). .
金属基板（１１）（１２）は０．５〜１．０皿厚の良熱
伝導性のアルミニウムで形成され、エボキシ樹脂等の接
着剤により基板（１１）（１２）を夫々の厚みだけ離間
させてポリイミド等の絶縁フイルム（１３）で接続する
。絶縁フィルム（１３）の反対主面には導電路（１４）
となる銅箔を貼着しておき、銅箔を選択的にエッチング
して所望形状の導電路（１４〉を形成する。The metal substrates (11) and (12) are made of aluminum with good thermal conductivity and have a plate thickness of 0.5 to 1.0 mm, and the substrates (11 and 12) are separated by their respective thicknesses using an adhesive such as epoxy resin. Connect with an insulating film (13) made of polyimide or the like. There is a conductive path (14) on the opposite main surface of the insulating film (13).
A copper foil is pasted on the substrate, and the copper foil is selectively etched to form a conductive path (14) in a desired shape.
導電路（１４）は第１図からも明らかな様に一方の基板
（１２）の端部に外部リード（１６）を半田付けするパ
ッド（１７）を並べ、パッド（１７）から導電路（１４
）を絶縁フィルム（１３）上に延在させる。回路素子（
１５）を固着する導電路（１４）の部分は両方の基板（
１１）（１２）上に位置する様に設計し、基板（１１）
（１２）の離間部分には折曲げのため回路素子（１５）
を設けない。As is clear from FIG. 1, the conductive path (14) is formed by arranging pads (17) to which external leads (16) are soldered to the end of one substrate (12), and connecting the pads (17) to the conductive path (14).
) is extended on the insulating film (13). Circuit element (
The part of the conductive path (14) that fixes the substrate (15)
11) Designed to be located on (12), the board (11)
(12) has a circuit element (15) for bending.
is not provided.
ところで夫々の基板（１１）（１２）上に固着される回
路素子（１５）は選択して固着実装される。即ち、本発
明の混成集積回路は折曲げ構造とすることによって小型
化を目的とする。しかし、バッド（１７〉を夫々の金属
基板（１１）（１２）に形成すると、パッド（１７）の
大きさによって小型化にある程度の制約が発生する。そ
こで本発明ではバッド〈１７）を一方の基板（１２）の
みに設け、超小型化の混成集積回路の提供をする。そこ
で、パッド（１７）が設けられた一方の基板（１２）上
にはチップ抵抗、チップコンデンサー等のいわゆる受動
素子の回路素子（１５）が固着され、パッドが形成され
ない他方の基板（１１）上にはチップ状の集積回路素子
、あるいは能動素子の回路素子（１５）と上述した受動
素子の回路素子（１５）とが固着されている。By the way, the circuit elements (15) to be fixed on the respective substrates (11, 12) are selectively and fixedly mounted. That is, the hybrid integrated circuit of the present invention aims to be miniaturized by having a folded structure. However, if the pads (17) are formed on the respective metal substrates (11) and (12), there will be some restrictions on miniaturization depending on the size of the pads (17).Therefore, in the present invention, the pads (17) are formed on one of the metal substrates (11) and (12). It is provided only on the substrate (12) to provide an ultra-miniaturized hybrid integrated circuit. Therefore, circuit elements (15), which are so-called passive elements such as chip resistors and chip capacitors, are fixed on one substrate (12) on which pads (17) are provided, and on the other substrate (11) on which no pads are formed. A chip-shaped integrated circuit element or an active element circuit element (15) and the above-mentioned passive element circuit element (15) are fixed to the substrate.
夫々の基板（１１）（１２）上に回路素子（１５）を組
込んだ後、基板（１１）（１２）の離間部分で絶縁フィ
ルム（１３）を折曲げて第３図に示す如く、基板（１１
バ１２）の夫々の反対主面をちょうど当接させて、接着
剤で固着するか、あるいは外部リードク１６）を残して
全体を樹脂（１８）でモールドする。After assembling the circuit elements (15) onto the respective substrates (11, 12), the insulating film (13) is bent at the separated parts of the substrates (11, 12) to form the substrates as shown in FIG. (11
The opposite major surfaces of each bar 12) are brought into close contact and fixed with adhesive, or the whole is molded with resin (18), leaving an external lead dot 16).
（ト）発明の効果
本発明に依れば、一方の金属基板のみにパッドを設ける
ことにより、他方の金属基板上の実装面積が大きく使用
できるのでチップ状の集積回路素子等の回路素子の実装
ができる。その結果、超小型化の混成集積回路を提供す
ることができる。また従来と同じ集積度を有する混成集
積回路を約半分の高さにでき、且つフレキシブルな絶縁
フイルム（１３）を採用することによって両基板（１１
）＜１２）の導電路（１４）の接続も不要となり従来と
同様の方法で製造できる。この結果従来では基板の片面
利用であったものが、木発明では基板の両面利用と等価
となり混成集積回路の小型化に大きく寄与できる。(G) Effects of the Invention According to the present invention, by providing pads only on one metal substrate, a large mounting area on the other metal substrate can be used for mounting circuit elements such as chip-shaped integrated circuit elements. I can do it. As a result, an ultra-miniaturized hybrid integrated circuit can be provided. In addition, the height of a hybrid integrated circuit with the same degree of integration as that of a conventional circuit can be reduced to about half, and by using a flexible insulating film (13), both substrates (11
) < 12) The connection of the conductive path (14) is also no longer necessary, and it can be manufactured by the same method as the conventional method. As a result, while conventionally one side of the board was used, the present invention is equivalent to using both sides of the board, which can greatly contribute to miniaturization of hybrid integrated circuits.
第１図は本発明による混成集積回路を説明する平面図、
第２図はその側面図、第３図は本発明の完成した混成集
積回路の断面図、第４図は従来の混成集積回路を示す平
面図、第５図はその側面図である。
ｍ）（１２）は金属基板、 （１３）は絶縁フィルム、
（１４）は導電路、 （１５）は回路素子、 （１６）
は外部ノード、 （１７）はパッド、 〈１８〉は
樹脂である。FIG. 1 is a plan view illustrating a hybrid integrated circuit according to the present invention;
FIG. 2 is a side view thereof, FIG. 3 is a sectional view of a completed hybrid integrated circuit according to the present invention, FIG. 4 is a plan view showing a conventional hybrid integrated circuit, and FIG. 5 is a side view thereof. m) (12) is a metal substrate, (13) is an insulating film,
(14) is a conductive path, (15) is a circuit element, (16)
is an external node, (17) is a pad, and <18> is a resin.
Claims (1)
絶縁フィルムと該フィルム上に設けた所望形状の導電路
と前記二枚の金属基板上の導電路上に固着される複数の
チップ状の回路素子とを具備し、前記両基板間の前記絶
縁フィルムを曲折して前記基板の反対主面を接する様に
配置し、前記両基板に設けた回路素子を前記絶縁フィル
ムの曲折部分上に延在される導電路を介して接続し、一
方の前記金属基板の端部のみに外部との接続を行うパッ
ドを設け、他方の前記金属基板上にチップ状の集積回路
素子あるいは能動素子の回路素子を選択して配置したこ
とを特徴とする混成集積回路。(1) Two metal substrates, an insulating film that connects the metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of chips fixed on the conductive paths on the two metal substrates. the insulating film between the two substrates is bent so that the opposite main surfaces of the substrates are in contact with each other, and the circuit element provided on both the substrates is placed on the bent portion of the insulating film. A pad for connection with the outside is provided only at the end of one of the metal substrates, and a chip-shaped integrated circuit element or an active element is provided on the other metal substrate. A hybrid integrated circuit characterized by a selected arrangement of circuit elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2109111A JPH02290093A (en) | 1990-04-25 | 1990-04-25 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2109111A JPH02290093A (en) | 1990-04-25 | 1990-04-25 | Hybrid integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19347686A Division JPS62115761A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02290093A true JPH02290093A (en) | 1990-11-29 |
Family
ID=14501843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2109111A Pending JPH02290093A (en) | 1990-04-25 | 1990-04-25 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02290093A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4822747B1 (en) * | 1970-12-10 | 1973-07-09 | ||
| JPS5225264A (en) * | 1975-08-21 | 1977-02-25 | Matsushita Electric Ind Co Ltd | Hybrid miniature parts |
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
-
1990
- 1990-04-25 JP JP2109111A patent/JPH02290093A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4822747B1 (en) * | 1970-12-10 | 1973-07-09 | ||
| JPS5225264A (en) * | 1975-08-21 | 1977-02-25 | Matsushita Electric Ind Co Ltd | Hybrid miniature parts |
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
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