JPS62149145A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS62149145A JPS62149145A JP61193474A JP19347486A JPS62149145A JP S62149145 A JPS62149145 A JP S62149145A JP 61193474 A JP61193474 A JP 61193474A JP 19347486 A JP19347486 A JP 19347486A JP S62149145 A JPS62149145 A JP S62149145A
- Authority
- JP
- Japan
- Prior art keywords
- substrates
- insulating film
- integrated circuit
- hybrid integrated
- conductive path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は混成集積回路に関し、特に折曲げ構造の混成集
積回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to improvements in a hybrid integrated circuit having a folded structure.
(ロ)従来の技術
従来の混成集積回路は第4図に示す如く、金属基板(1
)の−主面に絶縁薄層を設けて所望の導電路(2)を設
け、導電路(2)上に半導体集積回路、チップ抵抗ある
いはチップコンデンサー等の回路素子(3)を固着して
、第5図の如く外部リード(4)のみを残して全体を樹
脂(5)でモールドして形成していた。(B) Conventional technology A conventional hybrid integrated circuit has a metal substrate (one
), a desired conductive path (2) is provided by providing a thin insulating layer on the main surface of the conductive path (2), and a circuit element (3) such as a semiconductor integrated circuit, a chip resistor or a chip capacitor is fixed on the conductive path (2), As shown in FIG. 5, the entire structure was molded with resin (5), leaving only the external leads (4).
(ハ)発明が解決しようとする問題点
断る混成集積回路は金属基板(1)の−主面に形成され
るため、ある程度の集積度を確保するには高さが必要と
なり、電子機器の薄型化設計の難点となっていた。この
原因は主として外部リード(4)の固着パッド(6)に
かなりの面積が必要となるためである。(c) Problems to be Solved by the Invention Since hybrid integrated circuits are formed on the -main surface of the metal substrate (1), a certain height is required to ensure a certain degree of integration, and the thinness of electronic devices This was a difficult point in the design. This is mainly due to the fact that the fixing pad (6) of the external lead (4) requires a considerable area.
(ニ)問題点を解決するための手段
本発明は上述した点に鑑みてなされたものであり、第1
図及び第2図に示す如く、離間した二枚の同一形状の金
属基板(11)<12)を絶縁フィルム(13)で結合
させ、絶縁フィルム(13)上に所望形状の導電路(1
4)を設け、金属基板(11)(12)上の導電路(1
3)上に回路素子(15)を設けて基板(11)(12
)間の絶縁フィルム(13)を曲折許せて基板(11)
(12)の反対主面を当接配置きせる。(d) Means for solving the problems The present invention has been made in view of the above-mentioned points.
As shown in the figure and FIG.
4) and conductive paths (1) on the metal substrates (11) and (12).
3) A circuit element (15) is provided on the substrate (11) (12).
) to allow bending of the insulating film (13) between the substrates (11)
(12) The opposite main surfaces are placed in contact with each other.
(ホ)作用
斯上の如く、離間した同一形状の二枚の金属基板を絶縁
フィルムで結合し、絶縁フィルム上に導電路を設け、二
枚の基板上の導電路上に回路素子を設け、基板間の絶縁
フィルムを曲折許せて夫々基板の反対主面を接する様に
配置することで、夫々の基板の反対主面がピッタリと接
すると共に混成集積回路の高さを従来の半分にすること
ができる。(e) Operation As described above, two metal substrates of the same shape separated from each other are bonded with an insulating film, a conductive path is provided on the insulating film, a circuit element is provided on the conductive path on the two substrates, and the board By allowing the insulating film between the two to bend and arranging the opposite major surfaces of the respective substrates so that they are in contact, the opposite major surfaces of the respective substrates can be brought into perfect contact and the height of the hybrid integrated circuit can be halved compared to the conventional one. .
(へ)実施例
以下に第1図及び第2図に示した実施例に基づい工本発
明を詳述する。(f) Examples The present invention will be described in detail below based on the examples shown in FIGS. 1 and 2.
本発明の混成集積回路は第1図および第2図に示す如く
、二枚の金属基板(11)<12)と、基板(11)(
12〉を接続する絶縁フィルム(13)と、フィルム(
13)上に設けた導電路り14)と、導電路り14)上
に固着した半導体集積回路、チップ抵抗あるいはチップ
コンデンサー等の複数の回路素子(15)とを具備して
いる。As shown in FIGS. 1 and 2, the hybrid integrated circuit of the present invention includes two metal substrates (11) < 12) and a substrate (11) (
12> and an insulating film (13) that connects the film (
13) It comprises a conductive path 14) provided on the conductive path 14) and a plurality of circuit elements (15) such as a semiconductor integrated circuit, a chip resistor, or a chip capacitor fixed on the conductive path 14).
金属基板(11)け2)は第2図に示す如く、夫々同一
形状の0.5〜1.0■厚の良熱伝導性のアルミニウム
で形成され、エポキシ樹脂等の接着剤により基板(11
)(12)を夫々の厚みだけ離間させてポリイシド等の
絶縁フィルム(13)で接続する。絶縁フィルム(13
)の反対主面には導電路<14)となる銅箔を貼着して
おき、銅箔を選択的にエツチングして所望形状の導電路
り14)を形成する。導電路(14)−は第1図からも
明らかな様に一方の基板(12)の端部に外部リード(
16)を半田付けするパッド(17)を並べ、パッド(
17)から導電路(14〉を絶縁フィルム(13)上に
延在させる。回路素子(15)を固着する導電路(14
)の部分は両方の基板m)(12)上に位置する様に設
計し、基板(11)(12)の離間部分には折曲げのた
め回路素子(15)を設けない。As shown in Fig. 2, the metal substrates (11) (2) are made of aluminum with good thermal conductivity and have the same shape and a thickness of 0.5 to 1.0 cm.
) (12) are spaced apart by their respective thicknesses and connected with an insulating film (13) made of polyamide or the like. Insulating film (13
A copper foil serving as a conductive path <14) is pasted on the opposite main surface of the conductive path 14), and the copper foil is selectively etched to form a conductive path 14) of a desired shape. As is clear from FIG. 1, the conductive path (14) is connected to an external lead (
Line up the pads (17) to which you want to solder the pads (16)
A conductive path (14>) is extended from 17) onto the insulating film (13).The conductive path (14) to which the circuit element (15) is fixed
) is designed to be located on both substrates m) (12), and no circuit element (15) is provided in the separated portion of the substrates (11) and (12) due to bending.
回路素子(15)を組込んだ後、基板(11)(12)
の離間部分で絶縁フィルム(13)を折曲げて第3図に
示す如く、基板(11)(12)の夫々の反対主面をち
ょうど当接させて、外部リード(16)を残して全体を
樹脂(18)でモールドする。After incorporating the circuit element (15), the board (11) (12)
Fold the insulating film (13) at the spaced apart part and bring the opposite main surfaces of the substrates (11 and 12) into contact with each other as shown in Figure 3, leaving the external leads (16) intact. Mold with resin (18).
(ト)発明の効果
本発明に依れば、同一形状の二枚の金属基板を折曲げ配
置することにより夫々の基板の反対主面がピッタリと当
接すると共に従来と同じ集積度を有する混成集積回路を
約半分の高さにでき、且つフレキシブルな絶縁フィルム
(13)を採用することによって両基板m>(12)の
導電路(14)の接続も不要となり従来と同様の方法で
製造できる。この結果従来では基板の片面利用であった
ものが、本発明では基板の両面利用と等価となり混成集
積回路の小型化に大きく寄与できる。(G) Effects of the Invention According to the present invention, by bending and arranging two metal substrates of the same shape, the opposite main surfaces of each substrate are brought into perfect contact with each other, and a hybrid assembly having the same degree of integration as the conventional one can be achieved. The height of the circuit can be reduced to about half, and by using a flexible insulating film (13), there is no need to connect the conductive path (14) of both substrates m>(12), and the circuit can be manufactured using the same method as before. As a result, in the past, one side of the substrate was used, but in the present invention, it is equivalent to using both sides of the substrate, which can greatly contribute to miniaturization of hybrid integrated circuits.
第1図は本発明による混成集積回路を説明する平面図、
第2図はその側面図、第3図は本発明の完成した混成集
積回路の断面図、第4図は従来の混成集積回路を示す平
面図、第5図はその側面図である。
(11)(12)は金属基板、(13〉は絶縁フィルム
、(14)は導電路、(15)は回路素子、(16)は
外部り一ド、(17)はパッド、(18)は樹脂である
。FIG. 1 is a plan view illustrating a hybrid integrated circuit according to the present invention;
FIG. 2 is a side view thereof, FIG. 3 is a sectional view of a completed hybrid integrated circuit according to the present invention, FIG. 4 is a plan view showing a conventional hybrid integrated circuit, and FIG. 5 is a side view thereof. (11) (12) are metal substrates, (13> are insulating films, (14) are conductive paths, (15) are circuit elements, (16) are external leads, (17) are pads, (18) are It is resin.
Claims (1)
絶縁フィルムと該フィルム上に設けた所望形状の導電路
と該導電路上に固着される複数の回路素子とを具備し、
前記両金属基板を同一形状とし、前記両基板上の導電路
上のみに前記回路素子を設け、両基板間の絶縁フィルム
を曲折して前記基板の反対主面を接する様に配置し、前
記両基板に設けた回路素子を前記絶縁フィルムの曲折部
分上に延在される導電路を介して接続することを特徴と
する混成集積回路。(1) comprising two metal substrates, an insulating film that connects the metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements fixed on the conductive path,
Both the metal substrates have the same shape, the circuit element is provided only on the conductive path on the both substrates, and the insulating film between the two substrates is bent so that the opposite main surfaces of the substrates are in contact with each other, A hybrid integrated circuit characterized in that circuit elements provided in the insulating film are connected via conductive paths extending on the bent portions of the insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61193474A JPS62149145A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61193474A JPS62149145A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55169868A Division JPS6011809B2 (en) | 1980-12-01 | 1980-12-01 | hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62149145A true JPS62149145A (en) | 1987-07-03 |
Family
ID=16308616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61193474A Pending JPS62149145A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62149145A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4822747B1 (en) * | 1970-12-10 | 1973-07-09 | ||
JPS5225264A (en) * | 1975-08-21 | 1977-02-25 | Matsushita Electric Ind Co Ltd | Hybrid miniature parts |
JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
-
1986
- 1986-08-18 JP JP61193474A patent/JPS62149145A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4822747B1 (en) * | 1970-12-10 | 1973-07-09 | ||
JPS5225264A (en) * | 1975-08-21 | 1977-02-25 | Matsushita Electric Ind Co Ltd | Hybrid miniature parts |
JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
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