JPS62149147A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS62149147A JPS62149147A JP61193477A JP19347786A JPS62149147A JP S62149147 A JPS62149147 A JP S62149147A JP 61193477 A JP61193477 A JP 61193477A JP 19347786 A JP19347786 A JP 19347786A JP S62149147 A JPS62149147 A JP S62149147A
- Authority
- JP
- Japan
- Prior art keywords
- substrates
- insulating film
- integrated circuit
- hybrid integrated
- conductive path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は混成集積回路に関し、特に折曲げ構造の混成集
積回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to improvements in a hybrid integrated circuit having a folded structure.
（ロ）従来の技術
従来の混成集積回路は第４図に示す如く、金属基板（１
）の−主面に絶縁薄層を設けて所望の導電路（２）を設
け、導電路（２）上に半導体集積回路、チップ抵抗ある
いはチップコンデンサー等の回路素子（３）を固着して
、第５図の如く外部リード（４）のみを残して全体を樹
脂（５〉でモールドして形成していた。(B) Conventional technology A conventional hybrid integrated circuit has a metal substrate (one
), a desired conductive path (2) is provided by providing a thin insulating layer on the main surface of the conductive path (2), and a circuit element (3) such as a semiconductor integrated circuit, a chip resistor or a chip capacitor is fixed on the conductive path (2), As shown in FIG. 5, the entire structure was molded with resin (5), leaving only the external leads (4).
（ハ）発明が解決しようとする問題点
断る混成集積回路は金属基板（１）の−主面に形成され
るため、ある程度の集積度を確保するには高言が必要と
なり、電子機器の薄型化設計の難点となっていた。こ′
の原因は主として外部リード。(c) Problems to be Solved by the Invention Since hybrid integrated circuits are formed on the -main surface of the metal substrate (1), high standards are required to ensure a certain degree of integration, and thinner electronic devices are required. This was a difficult point in the design. child'
This is mainly due to external leads.
（４）の固着パッド（６）にかなりの面積が必要となる
ためである。This is because the fixing pad (6) (4) requires a considerable area.
（ニ）問題点を解決するための手段
本発明は上述した点に鑑みてなきれたものであり、第１
図乃至第２図に示す如く、離間した二枚の金属基板（１
１）（１２）を絶縁フィルム（１３）で結合させ、絶縁
フィルム（１３）上に所望形状の導電路（１４）を設け
、導電路（１４）が延在される一方の金属基板（１２）
の端部にパッド（１７）を設け、そのパッド（１７）上
に外部回路との接続を行う外部リード（１６）を固着し
、基板（１１）（１２）の絶縁フィルム（１３）を曲折
して基板（１１）（１２）の反対主面を当接きせて外部
り一ド（１６）を残して全体をｍＪｌ（１ｓ）でモール
ドして解決する。(d) Means for solving the problems The present invention was developed in view of the above-mentioned problems.
As shown in Figures 2 and 2, two metal substrates (1
1) (12) are combined with an insulating film (13), a conductive path (14) of a desired shape is provided on the insulating film (13), and one metal substrate (12) on which the conductive path (14) is extended.
A pad (17) is provided at the end of the board, an external lead (16) for connection with an external circuit is fixed onto the pad (17), and the insulating film (13) of the board (11) (12) is bent. The problem is solved by bringing the opposite main surfaces of the substrates (11) and (12) into contact with each other and molding the entire body with mJl (1s), leaving the outer edge (16).
（ホ）作用
斯上の如く、離間した二枚の金属基板を絶縁フィルムで
結合し、絶縁フィルム上に設ける導電パッドを一方の金
属基板の端部に設けて、パッド上に外部リードを固着し
、夫々の基板の反対主面が当接する様に折曲げ外部リー
ドを残して全体を樹脂モールドすることにより、混成集
積回路の高さを半分にすることができ従来と同様に取扱
うことができる。(E) Operation As described above, two metal substrates separated from each other are connected with an insulating film, a conductive pad provided on the insulating film is provided at the end of one metal substrate, and an external lead is fixed on the pad. The height of the hybrid integrated circuit can be halved and it can be handled in the same way as before by bending the boards so that the opposite main surfaces of the circuit boards come into contact with each other and leaving the external leads and molding the entire circuit board with resin.
（へ）実施例
以下に第１図乃至第３図に示した実施例に基づいて本発
明を詳述する。(f) Examples The present invention will be described in detail below based on the examples shown in FIGS. 1 to 3.
本発明の混成集積回路は第１図および第２図に示す如く
、二枚の金属基板（１１）（１２）と、基板（１１）（
１２）を接続する絶縁フィルム（１３）と、フィルム（
１３）上に設けた導電路（１４）と、導電路（１４）上
に固着した半導体集積回路、チップ抵抗あるいはチップ
コンデンサー等の複数の回路素子（１５）とを具備して
いる。As shown in FIGS. 1 and 2, the hybrid integrated circuit of the present invention includes two metal substrates (11) (12) and a substrate (11) (
12) and an insulating film (13) that connects the film (
13) It includes a conductive path (14) provided on the conductive path (14) and a plurality of circuit elements (15) such as a semiconductor integrated circuit, a chip resistor, or a chip capacitor fixed on the conductive path (14).
金属基板（１１）＜１２）は０．５〜１．０ＩＩＩｍ厚
の良熱伝導性のアルミニウムで形成され、エポキシ樹脂
等の接着剤により基板（１１）（１２）を夫々の厚みだ
け離間させてポリイシド等の絶縁フィルム（１３）で接
続する。絶縁フィルム（１３）の反対主面には導電路（
１４）となる銅箔を貼着しておき、銅箔を選択的にエツ
チングして所望形状の導電路＜１４）を形成する。導電
路（１４）は第１図からも明らかな様に一方の基板（１
２〉の端部に外部リード（１６）を半田付けするパッド
（１７）を並べ、パッド（１７）から導電路（１４）を
絶縁フィルム（１３）上に延在させる。回路素子（１５
）を固着する導電路（１４）の部分は両方の基板（１１
）（１２）上に位置する様に設計し、基板（１１）（１
２）の離間部分には折曲げのため回路素子（１５）を設
けない。The metal substrates (11)<12) are made of aluminum with good thermal conductivity and have a thickness of 0.5 to 1.0IIIm, and the substrates (11) and (12) are separated by their respective thicknesses using an adhesive such as epoxy resin. Connect with an insulating film (13) made of polyamide or the like. A conductive path (
14) is pasted, and the copper foil is selectively etched to form a conductive path <14) in a desired shape. As is clear from FIG.
Pads (17) to which external leads (16) are soldered are lined up at the ends of 2>, and conductive paths (14) are extended from the pads (17) onto the insulating film (13). Circuit element (15
) is connected to both substrates (11
) (12), and the board (11) (1
No circuit element (15) is provided in the spaced apart portion of 2) due to bending.
回路素子（１５）を組込んだ後、基板（１１）（１２）
の離間部分で絶縁フィルム（１３）を折曲げて第３図に
示す如く、基板（１１）（１２）の夫々の反対主面をち
ょうど当接させて、外部リード（１６）を残して全体を
樹脂（１８）でモールドする。After incorporating the circuit element (15), the board (11) (12)
Fold the insulating film (13) at the spaced apart part and bring the opposite main surfaces of the substrates (11 and 12) into contact with each other as shown in Figure 3, leaving the external leads (16) intact. Mold with resin (18).
（ト）発明の効果
本発明に依れば、二枚の基板を折曲げ全体を樹脂モール
ドすることで、従来と同様に取扱いが行え更に、従来と
同じ集積度を有する混成集積回路を約半分の高さにでき
、且つフレキシブルな絶縁フィルム（１３）を採用する
ことによって内基板（１１）（１２）の導電路（１４）
の接続も不要となり従来と同様の方法で製造できる。こ
の結果従来では基板の片面利用であったものが、本発明
では基板の両面利用と等価となり混成集積回路の小型化
に大きく寄与できる。更に本発明では二枚の基板をモー
ルドするので従来よりも強固に支持ができるのでプリン
ト基板等へ実装した際、安定した実装が行える利点を有
するものである。(G) Effects of the Invention According to the present invention, by folding two substrates and molding the entire body with resin, it can be handled in the same way as before, and furthermore, the hybrid integrated circuit having the same degree of integration as the conventional one can be reduced by about half. By using a flexible insulating film (13), the conductive path (14) of the inner substrate (11) (12) can be
It also eliminates the need for connections, and can be manufactured using the same method as before. As a result, in the past, one side of the substrate was used, but in the present invention, it is equivalent to using both sides of the substrate, which can greatly contribute to miniaturization of hybrid integrated circuits. Furthermore, since two substrates are molded in the present invention, they can be supported more firmly than before, so when mounted on a printed circuit board or the like, it has the advantage of being able to perform stable mounting.
第１図は本発明による混成集積回路を説明する平面図、
第２図はその側面図、第３ＶＩＡは本発明の完成した混
成集積回路の断面図、第４図は従来の混成集積回路を示
す平面図、第５図はその側面図である。
（１１）（１２）は金属基板、（１３）は絶縁フィルム
、（１４）は導電路、（１５）は回路素子、（１６）は
外部リード、（１７〉はパッド、（１８）は樹脂である
。FIG. 1 is a plan view illustrating a hybrid integrated circuit according to the present invention;
FIG. 2 is a side view thereof, VIA 3 is a sectional view of a completed hybrid integrated circuit according to the present invention, FIG. 4 is a plan view showing a conventional hybrid integrated circuit, and FIG. 5 is a side view thereof. (11) (12) is a metal substrate, (13) is an insulating film, (14) is a conductive path, (15) is a circuit element, (16) is an external lead, (17> is a pad, and (18) is a resin. be.
Claims (1)
絶縁フィルムと該フィルム上に設けられた所望形状の導
電路と該導電路上に固着される複数の回路素子とを具備
し、両基板間の前記絶縁フィルムを曲折して前記基板の
反対主面を接する様に配置し、前記両基板に設けた回路
素子を前記絶縁フィルムの曲折部分上に延在される導電
路を介して接続し、前記一方の金属基板の端部に設けた
パッドに外部リードを固着し、前記外部リードを残して
全体を樹脂でモールドすることを特徴とする混成集積回
路。(1) comprising two metal substrates, an insulating film that connects the metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements fixed on the conductive path, The insulating film between both substrates is bent so that the opposite main surfaces of the substrates are in contact with each other, and the circuit elements provided on both substrates are connected via conductive paths extending on the bent portions of the insulating film. 1. A hybrid integrated circuit characterized in that an external lead is fixed to a pad provided at an end of the one metal substrate, and the entire circuit is molded with resin, leaving the external lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61193477A JPS62149147A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61193477A JPS62149147A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55169868A Division JPS6011809B2 (en) | 1980-12-01 | 1980-12-01 | hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62149147A true JPS62149147A (en) | 1987-07-03 |
Family
ID=16308670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61193477A Pending JPS62149147A (en) | 1986-08-18 | 1986-08-18 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62149147A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4822747B1 (en) * | 1970-12-10 | 1973-07-09 | ||
| JPS5225264A (en) * | 1975-08-21 | 1977-02-25 | Matsushita Electric Ind Co Ltd | Hybrid miniature parts |
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
-
1986
- 1986-08-18 JP JP61193477A patent/JPS62149147A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4822747B1 (en) * | 1970-12-10 | 1973-07-09 | ||
| JPS5225264A (en) * | 1975-08-21 | 1977-02-25 | Matsushita Electric Ind Co Ltd | Hybrid miniature parts |
| JPS5792852A (en) * | 1980-12-01 | 1982-06-09 | Sanyo Electric Co Ltd | Hybrid integrated circuit |
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