JPH0556658B2 - - Google Patents

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Publication number
JPH0556658B2
JPH0556658B2 JP24544984A JP24544984A JPH0556658B2 JP H0556658 B2 JPH0556658 B2 JP H0556658B2 JP 24544984 A JP24544984 A JP 24544984A JP 24544984 A JP24544984 A JP 24544984A JP H0556658 B2 JPH0556658 B2 JP H0556658B2
Authority
JP
Japan
Prior art keywords
hybrid integrated
integrated circuit
conductive path
metal substrate
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24544984A
Other languages
Japanese (ja)
Other versions
JPS61124144A (en
Inventor
Yoshio Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP59245449A priority Critical patent/JPS61124144A/en
Publication of JPS61124144A publication Critical patent/JPS61124144A/en
Publication of JPH0556658B2 publication Critical patent/JPH0556658B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15717—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400 C and less than 950 C
    • H01L2924/15724—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は混成集積回路、特に高密度集積化に適
した混成集積回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to hybrid integrated circuits, and particularly to improvements in hybrid integrated circuits suitable for high-density integration.

(ロ) 従来の技術 従来の混成集積回路は第４図に示す如く、金属
基板１の一主面に絶縁薄層を設けて所望の導電路
２を設け、導電路２上に半導体集積回路、チツプ
抵抗あるいはチツプコンデンサー等の回路素子３
を固着して、第５図の如く外部リード４のみを残
して全体を樹脂５でモールドして形成していた。(b) Prior Art As shown in FIG. 4, a conventional hybrid integrated circuit includes a thin insulating layer provided on one main surface of a metal substrate 1 to provide a desired conductive path 2, and a semiconductor integrated circuit, Circuit elements such as chip resistors or chip capacitors 3
was fixed, and the whole was molded with resin 5, leaving only the external leads 4, as shown in FIG.

斯る混成集積回路は金属基板１の一主面に形成
されるため、ある程度の集積度を確保するには高
さが必要となり、電子機器の薄型化設計の難点と
なつていた。この原因は主として外部リード４の
固着パツド６にかなりの面積が必要となるためで
ある。 Since such a hybrid integrated circuit is formed on one main surface of the metal substrate 1, a certain height is required to ensure a certain degree of integration, which has been a difficulty in designing thinner electronic devices. This is mainly due to the fact that the fixing pad 6 of the external lead 4 requires a considerable area.

本発明者は斯上の欠点を除去するために第６図
および第７図に示す混成集積回路を考えた。この
混成集積回路は２枚の金属基板１１，１２と、基
板１１，１２を接続する絶縁フイルム１３と、フ
イルム１３上に設けた導電路１４と、導電路１４
上に固着した半導体集積回路、チツプ抵抗あるい
はチツプコンデンサー等の複数の回路素子１５と
を具備し、基板１１，１２の離間部分で絶縁フイ
ルム１３を折り曲げて第７図の如くプリント基板
１６に実装される。この構造に依れば従来と同じ
集積度を有する混成集積回路を約半分の高さにで
きる利点を有する。 In order to eliminate the above-mentioned drawbacks, the inventor of the present invention devised a hybrid integrated circuit shown in FIGS. 6 and 7. This hybrid integrated circuit includes two metal substrates 11 and 12, an insulating film 13 connecting the substrates 11 and 12, a conductive path 14 provided on the film 13, and a conductive path 14 provided on the film 13.
It is equipped with a plurality of circuit elements 15 such as a semiconductor integrated circuit, a chip resistor, or a chip capacitor fixed thereon, and is mounted on a printed circuit board 16 by bending the insulating film 13 at the spaced part between the substrates 11 and 12, as shown in FIG. Ru. This structure has the advantage that a hybrid integrated circuit having the same degree of integration as the conventional one can be reduced in height to about half.

しかし折曲部分がフレキシブルな絶縁フイルム
１３であるので、折曲角度等の形状を定型化でき
ず自動挿入を行なえず、また絶縁フイルム１３で
の破断も発生するおそれがあつた。 However, since the bent portion is the flexible insulating film 13, the bending angle and other shapes cannot be standardized, making automatic insertion impossible, and there is also a risk that the insulating film 13 may break.

更に本発明者は斯上した欠点を除去するために
第８図、第９図および第１０図に示す混成集積回
路を考えた。この混成集積回路は金属基板２１
と、金属基板２１の折曲部分２０となる中央部に
設けた細長い切欠孔２２と、金属基板２１の折曲
部分２０の両端に金属基板２１をそのまま残存さ
せて設けた連結体２３と、金属基板２１表面に付
着した絶縁フイルム２４と、絶縁フイルム２４上
に設けた導電路２５と、導電路２５上に固着した
複数の回路素子２６とを具備し、絶縁フイルム２
４を連結体２３部分で切欠いている。斯る混成集
積回路は金属基板２１を折曲部分で曲折しても、
第９図の如く連結体２３が単に曲折されているだ
けで、絶縁フイルム２４のある曲折部分では第１
０図の如く切欠孔２２により絶縁フイルム２４が
引き伸ばされることなく基板２１を曲折できる。 Furthermore, in order to eliminate the above-mentioned drawbacks, the inventors have devised hybrid integrated circuits shown in FIGS. 8, 9, and 10. This hybrid integrated circuit has a metal substrate 21
, an elongated notch hole 22 provided in the center of the bent portion 20 of the metal substrate 21 , a connecting body 23 provided with the metal substrate 21 remaining as it is at both ends of the bent portion 20 of the metal substrate 21 , and a metal The insulating film 2 includes an insulating film 24 attached to the surface of the substrate 21, a conductive path 25 provided on the insulating film 24, and a plurality of circuit elements 26 fixed on the conductive path 25.
4 is cut out at the connecting body 23 portion. In such a hybrid integrated circuit, even if the metal substrate 21 is bent at the bent part,
As shown in FIG. 9, the connecting body 23 is simply bent, and in a certain bent part of the insulating film 24, the first
As shown in Figure 0, the notch hole 22 allows the substrate 21 to be bent without stretching the insulating film 24.

(ハ) 発明が解決しようとする問題点 しかしながら上述した混成集積回路はいずれも
絶縁フイルムを不可欠としており、絶縁フイルム
１３，２４は高価なポリイミド等を用いている。
このために混成集積回路は高価とならざるを得な
い欠点があつた。(c) Problems to be Solved by the Invention However, the above-mentioned hybrid integrated circuits all require an insulating film, and the insulating films 13 and 24 are made of expensive polyimide or the like.
For this reason, hybrid integrated circuits have had the disadvantage of being expensive.

(ニ) 問題点を解決するための手段 本発明は斯点に鑑みてなされ、絶縁被覆した導
線を用いて接続を行うことにより絶縁フイルムを
不要とした混成集積回路を実現するものである。(d) Means for Solving the Problems The present invention has been made in view of the above problems, and aims to realize a hybrid integrated circuit that eliminates the need for an insulating film by making connections using insulated conductive wires.

(ホ) 作用 本発明では絶縁被覆した導線が直接導電路に超
音波ボンデイング行なえる点に着目し、絶縁被覆
した導線で電極パツド間を接続している。(e) Effect The present invention focuses on the fact that an insulated conductive wire can be ultrasonically bonded directly to a conductive path, and connects electrode pads with an insulated conductive wire.

(ヘ) 実施例 本発明の一実施例を第１図乃至第３図を参照し
て詳述する。(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

金属基板２１は0.5〜1.0mm厚の良熱伝導性のア
ルミニウムで形成され、その表面は酸化アルミニ
ウム膜で被覆されている。金属基板３１の折曲部
分３０となる中央部にはプレス打抜きで設けた細
長い切欠孔３２と金属基板３１をそのまま残存さ
せた複数本の連結体３３を設ける。連結体３３は
金属基板３１を一体的に支持し、折曲げても定型
を保持する働きを有する。 The metal substrate 21 is made of aluminum with good thermal conductivity and has a thickness of 0.5 to 1.0 mm, and its surface is coated with an aluminum oxide film. At the center of the metal substrate 31, which is the bent portion 30, there are provided an elongated notch hole 32 formed by press punching and a plurality of connecting bodies 33 in which the metal substrate 31 remains as it is. The connecting body 33 has the function of integrally supporting the metal substrate 31 and maintaining its regular shape even when bent.

金属基板３１の酸化アルミニウム膜表面には導
電路３４となる銅箔を貼着しておき、この銅箔を
選択的にエツチングして所望形状の導電路３４を
形成する。導電路３４は第１図から明らかな様に
両端に実装するプリント基板の電極に半田付けす
るパツド３５を複数個配列し、パツド３５から導
電路３４を酸化アルミニウム膜上を所望パターン
に延在させる。また切欠孔３２の対向する側面に
は電極パツド３６を設けており、対応する電極パ
ツド３６との接続を行う。 A copper foil serving as a conductive path 34 is pasted on the surface of the aluminum oxide film of the metal substrate 31, and this copper foil is selectively etched to form a conductive path 34 of a desired shape. As is clear from FIG. 1, the conductive path 34 is formed by arranging a plurality of pads 35 soldered to the electrodes of the printed circuit board mounted on both ends, and extends the conductive path 34 from the pads 35 in a desired pattern on the aluminum oxide film. . Moreover, electrode pads 36 are provided on opposite sides of the notch hole 32, and connections are made with the corresponding electrode pads 36.

回路素子３７は所望の導電路３４上に半田付け
される。回路素子３７が固着される導電路３４の
部分は基板３１全体に位置する様に設計し、基板
３１の折曲部分を除いて半導体集積回路、チツプ
抵抗あるいはチツプコンデンサー等の複数の回路
素子を組み込む。 Circuit elements 37 are soldered onto desired conductive paths 34. The portion of the conductive path 34 to which the circuit element 37 is fixed is designed to be located on the entire substrate 31, and a plurality of circuit elements such as a semiconductor integrated circuit, a chip resistor, or a chip capacitor are incorporated in the portion of the substrate 31 excluding the bent portion. .

本発明の特徴は切欠孔３２の両側に設けた電極
パツド３６を絶縁被覆した導線３８で接続するこ
とにある。本発明に用いる導線は第３図に示す如
く、50〜200μφの銅細線３９とその表面を被覆す
るウレタンあいるは弗化エチレンより成る絶縁被
膜４０で形成されている。絶縁被膜４０は銅細線
３９をウレタンあるいは弗化エチレン溶液中を通
して10〜50μ厚（平均的には20μ厚）に付着した
ものである。斯る導線３８は超音波ボンデイング
装置を用いて電極パツド３６に超音波振動により
固着する。導線３８は断面円形の銅細線を用いて
いるので、導電路３４との接点に超音波振動のエ
ネルギーが集中して絶縁被膜４０が破れて銅細線
が露出される。そして銅細線と銅の導電路３４と
の同一材料の結合により超音波ボンデイングでき
る。 A feature of the present invention is that the electrode pads 36 provided on both sides of the cutout hole 32 are connected by conductive wires 38 coated with insulation. As shown in FIG. 3, the conductive wire used in the present invention is formed of a thin copper wire 39 of 50 to 200 .mu.φ and an insulating coating 40 made of urethane or fluorinated ethylene covering the surface thereof. The insulating coating 40 is made by passing thin copper wires 39 through a urethane or fluorinated ethylene solution and depositing them to a thickness of 10 to 50 .mu.m (20 .mu.m thick on average). The conductive wire 38 is fixed to the electrode pad 36 by ultrasonic vibration using an ultrasonic bonding device. Since the conducting wire 38 is a thin copper wire with a circular cross section, the energy of the ultrasonic vibration is concentrated at the point of contact with the conductive path 34, and the insulating coating 40 is torn, exposing the thin copper wire. Ultrasonic bonding can be performed by bonding the thin copper wire and the copper conductive path 34 using the same material.

斯上した本発明による混成集積回路では電極パ
ツド３６間を接続する導線３８は絶縁被膜４０で
覆われているので、導線３８同志が短絡するおそ
れもなくまた基板３１とも短絡するおそれがな
い。この結果従来用いていた高価な絶縁フイルム
を廃止でき、安価なボンデイングワイヤを利用で
きる。そして超音波ボンデイング装置を利用する
ことにより自動ボンデイングも可能である。 In the above-described hybrid integrated circuit according to the present invention, the conductive wires 38 connecting between the electrode pads 36 are covered with the insulating coating 40, so that there is no risk of the conductive wires 38 shorting each other or with the substrate 31. As a result, the expensive insulating film conventionally used can be eliminated, and inexpensive bonding wires can be used. Automatic bonding is also possible by using an ultrasonic bonding device.

第２図は本発明による混成集積回路をプリント
基板に実装した断面を示している。図面から明ら
かな様に、切欠孔３２で基板３１を折曲げて、プ
リント基板へ半田付けしている。導線３８は基板
３１の折曲げに応じて変形し且つ絶縁被覆してい
るので短絡のおそれもない。 FIG. 2 shows a cross section of a hybrid integrated circuit according to the present invention mounted on a printed circuit board. As is clear from the drawing, the board 31 is bent at the notch hole 32 and soldered to the printed circuit board. Since the conductive wire 38 deforms in accordance with the bending of the substrate 31 and is coated with insulation, there is no risk of short circuit.

(ト) 発明の効果 本発明に依れば、従来と同じ集積度を有する混
成集積回路を約半分の高さで実現でき且つ高価な
フレキシブルな絶縁フイルムを用いる必要もなく
なる。(G) Effects of the Invention According to the present invention, a hybrid integrated circuit having the same degree of integration as the conventional circuit can be realized at about half the height, and there is no need to use an expensive flexible insulating film.

更に絶縁被覆した導線３８を用いるので超音波
ボンデイングでき極めて容易に電極パツド３６間
の接続を行なえる。 Further, since the conducting wire 38 coated with insulation is used, ultrasonic bonding can be performed, and the connection between the electrode pads 36 can be made very easily.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の混成集積回路を説明する平面
図、第２図は本発明の混成集積回路を実装した側
面断面図、第３図は本発明に用いる絶縁被覆した
導線を説明する断面図、第４図は従来の混成集積
回路を説明する平面図、第５図は第４図の側面断
面図、第６図は従来の改良した混成集積回路を説
明する平面図、第７図は第６図の混成集積回路を
実装した側面断面図、第８図は更に改良をした従
来の混成集積回路を説明する平面図、第９図およ
び第１０図は第８図の混成集積回路の側面断面図
である。 主な図番の説明、３１は金属基板、３２は切欠
孔、３３は連結体、３４は導電路、３６は電極パ
ツド、３７は回路素子、３８は導線である。 FIG. 1 is a plan view illustrating the hybrid integrated circuit of the present invention, FIG. 2 is a sectional side view of the hybrid integrated circuit of the present invention mounted, and FIG. 3 is a sectional view illustrating an insulated conductor used in the present invention. , FIG. 4 is a plan view illustrating a conventional hybrid integrated circuit, FIG. 5 is a side sectional view of FIG. 4, FIG. 6 is a plan view illustrating a conventional improved hybrid integrated circuit, and FIG. 6 is a side cross-sectional view of the hybrid integrated circuit mounted, FIG. 8 is a plan view illustrating a further improved conventional hybrid integrated circuit, and FIGS. 9 and 10 are side cross-sectional views of the hybrid integrated circuit of FIG. It is a diagram. Explanation of main figure numbers: 31 is a metal substrate, 32 is a notch hole, 33 is a connecting body, 34 is a conductive path, 36 is an electrode pad, 37 is a circuit element, and 38 is a conductive wire.

Claims (1)

【特許請求の範囲】[Claims] １ 金属基板と、該金属基板の折曲部分に設けた
切欠孔と前記基板を一体化する連結体と、前記金
属基板表面上の絶縁薄層上に設けた所望の導電路
と、該導電路上に固着された複数の回路素子とを
具備し、前記切欠孔の両側に対向して電極パツド
を設け、該電極パツドを絶縁被覆した導線で接続
することを特徴とする混成集積回路。1. A metal substrate, a connecting body that integrates the substrate with a cutout hole provided in a bent portion of the metal substrate, a desired conductive path provided on an insulating thin layer on the surface of the metal substrate, and a conductive path provided on the conductive path. 1. A hybrid integrated circuit comprising: a plurality of circuit elements fixed to a plurality of circuit elements; electrode pads are provided opposite to each other on both sides of the notch hole; and the electrode pads are connected with an insulated conductive wire.
JP59245449A 1984-11-20 1984-11-20 Hybrid integrated circuit Granted JPS61124144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59245449A JPS61124144A (en) 1984-11-20 1984-11-20 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59245449A JPS61124144A (en) 1984-11-20 1984-11-20 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS61124144A JPS61124144A (en) 1986-06-11
JPH0556658B2 true JPH0556658B2 (en) 1993-08-20

Family

ID=17133825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59245449A Granted JPS61124144A (en) 1984-11-20 1984-11-20 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS61124144A (en)

Also Published As

Publication number Publication date
JPS61124144A (en) 1986-06-11

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