JPS60106339U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60106339U
JPS60106339U JP1983203826U JP20382683U JPS60106339U JP S60106339 U JPS60106339 U JP S60106339U JP 1983203826 U JP1983203826 U JP 1983203826U JP 20382683 U JP20382683 U JP 20382683U JP S60106339 U JPS60106339 U JP S60106339U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
terminals
terminal
heat dissipation
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983203826U
Other languages
English (en)
Inventor
林　良茂
茂成 高見
達彦 入江
二郎 橋爪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1983203826U priority Critical patent/JPS60106339U/ja
Publication of JPS60106339U publication Critical patent/JPS60106339U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図乃至第５図はこの考案の従来例を示す図で、第１
図は平面図、第２図は断面図、第３図は斜視図、第４図
及び第５図は平面図、第６図乃至第１１図はこの考案の
一実施例を示す図で第６図は平面図、第７図は第６図の
側面図、第８図は平面図、第９図は第８図のＡ−Ａ矢視
図、第１０図は第８図のＢ−Ｂ矢視図、第１１図は斜視
図である。　□

Claims (1)

    【実用新案登録請求の範囲】
  1. 放熱フィン１の両側にそって端子２を平行に配し、放熱
    フィン１上に半導体素子３を塔載して接続すると共に該
    半導体素子３と端子２とをワイヤー７で接続し、放熱フ
    ィン１及び端子２の裏面を残して樹脂封止して成ること
    を特徴とする半導体装置。
JP1983203826U 1983-12-23 1983-12-23 半導体装置 Pending JPS60106339U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983203826U JPS60106339U (ja) 1983-12-23 1983-12-23 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983203826U JPS60106339U (ja) 1983-12-23 1983-12-23 半導体装置

Publications (1)

Publication Number Publication Date
JPS60106339U true JPS60106339U (ja) 1985-07-19

Family

ID=30766231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983203826U Pending JPS60106339U (ja) 1983-12-23 1983-12-23 半導体装置

Country Status (1)

Country Link
JP (1) JPS60106339U (ja)

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