JPS6094834U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6094834U
JPS6094834U JP1983187140U JP18714083U JPS6094834U JP S6094834 U JPS6094834 U JP S6094834U JP 1983187140 U JP1983187140 U JP 1983187140U JP 18714083 U JP18714083 U JP 18714083U JP S6094834 U JPS6094834 U JP S6094834U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
back surface
semiconductor
recorded
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983187140U
Other languages
English (en)
Inventor
有岡　貞治郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1983187140U priority Critical patent/JPS6094834U/ja
Publication of JPS6094834U publication Critical patent/JPS6094834U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads

Landscapes

  • Thyristors (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
図は本考案実施例の断面図を示し、１はヘッダ、２はペ
レット、３はハンダ、９は凹みであ　　−る。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体ペレットの裏面に凹みを設け、斯かる裏″　　面
    をハンダを介してヘッダに一着したことを特徴−とする
    半導体装置。
JP1983187140U 1983-12-02 1983-12-02 半導体装置 Pending JPS6094834U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983187140U JPS6094834U (ja) 1983-12-02 1983-12-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983187140U JPS6094834U (ja) 1983-12-02 1983-12-02 半導体装置

Publications (1)

Publication Number Publication Date
JPS6094834U true JPS6094834U (ja) 1985-06-28

Family

ID=30404029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983187140U Pending JPS6094834U (ja) 1983-12-02 1983-12-02 半導体装置

Country Status (1)

Country Link
JP (1) JPS6094834U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203489A (ja) * 2000-01-18 2001-07-27 Oki Electric Ind Co Ltd シールドケースの実装構造

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203489A (ja) * 2000-01-18 2001-07-27 Oki Electric Ind Co Ltd シールドケースの実装構造

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