JPS5999750A - Ｉｃ用リ−ドフレ−ムの製造方法 - Google Patents

Ｉｃ用リ−ドフレ−ムの製造方法

Info

Publication number
JPS5999750A
JPS5999750A JP20865982A JP20865982A JPS5999750A JP S5999750 A JPS5999750 A JP S5999750A JP 20865982 A JP20865982 A JP 20865982A JP 20865982 A JP20865982 A JP 20865982A JP S5999750 A JPS5999750 A JP S5999750A
Authority
JP
Japan
Prior art keywords
plating
plated
lead
hole
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20865982A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0141034B2 (enrdf_load_stackoverflow
Inventor
Yasuzo Arino
有野　靖三
Muneyuki Hasemi
長谷見　統之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP20865982A priority Critical patent/JPS5999750A/ja
Publication of JPS5999750A publication Critical patent/JPS5999750A/ja
Publication of JPH0141034B2 publication Critical patent/JPH0141034B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP20865982A 1982-11-30 1982-11-30 Ｉｃ用リ−ドフレ−ムの製造方法 Granted JPS5999750A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20865982A JPS5999750A (ja) 1982-11-30 1982-11-30 Ｉｃ用リ−ドフレ−ムの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20865982A JPS5999750A (ja) 1982-11-30 1982-11-30 Ｉｃ用リ−ドフレ−ムの製造方法

Publications (2)

Publication Number Publication Date
JPS5999750A true JPS5999750A (ja) 1984-06-08
JPH0141034B2 JPH0141034B2 (enrdf_load_stackoverflow) 1989-09-01

Family

ID=16559912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20865982A Granted JPS5999750A (ja) 1982-11-30 1982-11-30 Ｉｃ用リ−ドフレ−ムの製造方法

Country Status (1)

Country Link
JP (1) JPS5999750A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188952A (ja) * 1983-04-11 1984-10-26 Shinko Electric Ind Co Ltd リ−ドフレ−ムの製造方法
US6047467A (en) * 1995-10-12 2000-04-11 Vlsi Technology, Inc. Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188952A (ja) * 1983-04-11 1984-10-26 Shinko Electric Ind Co Ltd リ−ドフレ−ムの製造方法
US6047467A (en) * 1995-10-12 2000-04-11 Vlsi Technology, Inc. Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads

Also Published As

Publication number Publication date
JPH0141034B2 (enrdf_load_stackoverflow) 1989-09-01

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