JPS5999750A - Manufactue of lead frame for ic - Google Patents

Manufactue of lead frame for ic

Info

Publication number
JPS5999750A
JPS5999750A JP20865982A JP20865982A JPS5999750A JP S5999750 A JPS5999750 A JP S5999750A JP 20865982 A JP20865982 A JP 20865982A JP 20865982 A JP20865982 A JP 20865982A JP S5999750 A JPS5999750 A JP S5999750A
Authority
JP
Japan
Prior art keywords
plating
plated
lead
hole
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20865982A
Other languages
Japanese (ja)
Other versions
JPH0141034B2 (en
Inventor
Yasuzo Arino
有野 靖三
Muneyuki Hasemi
長谷見 統之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP20865982A priority Critical patent/JPS5999750A/en
Publication of JPS5999750A publication Critical patent/JPS5999750A/en
Publication of JPH0141034B2 publication Critical patent/JPH0141034B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports

Abstract

PURPOSE:To reduce the number of unsatisfactroy products by a method wherein a positioning hole is provided on both sides of a metal stripe, and a plating position discriminating hole is formed in the center part, thereby enabling to discriminate the positional deviation of plating after the plating has been performed. CONSTITUTION:A positioning pin hole 8 is provided on both sides of a metal stripe 7 and channel-like through holes 10 and 11 are formed in the center part 9. The holes 10 and 11 are coincided with the gap located between a lead 2 and an island 3. When a precisous metal plating is performed at the center part 9, the tip of the lead 2 and the island 3 are also plated. If the plated metal stripe is checked, the relations between the holes 10 and 11 and the plated position can be find out immediately, and the production of unsatisfactory articles due to positional deviation can be reduced to minimum. When the partially plated metal stripe 7 is punched out using the hole 8, the lead frame with a plated layer on the upper surface and the end face of the lead 2 and having no plated layer at all on both side faces can be obtained.

Description

【発明の詳細な説明】 本発明はIC用リードフレームの製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing an IC lead frame.

半導体集積回路(IC)素子のパッケージ材料として、
例えば第1図に示すようなリードフレーム1が用いられ
ている。このリードフレーム1は樹月旨モールド形DI
P (Dual In1ine Pack・@geの略
)用のもので、多数のリード2の群とIC素子搭載部(
以下、「アイランド」という)3瀘複数組連続的に形成
されている。上記リードフレーム1は通常第2図に示す
ようにアイランド3及びリード2の内側先署部に金、銀
等の貴金属メッキが施されてIC素子のパッケージ(供
される。このようなリードフレーム1は、金属板又は金
属条をフォトエツチングまたはプレス打抜きによシリー
ド2及びアイランド3を)形成した%PJr4Jの部分
に貴金属をメッキ、するのが一般的である。所要の部分
にのみメッキする部分メッキ装置は、例えば特公昭49
72.47751号公報に記載のように、メッキすべき
部分全透孔としたマスク板と抑圧板とで被メッキ材を挾
持し、この透孔にメッキ液を噴射すると同時に被メッキ
材(陰極)と陽極との間に通電スるようになっている。
As a packaging material for semiconductor integrated circuit (IC) elements,
For example, a lead frame 1 as shown in FIG. 1 is used. This lead frame 1 is Kizuki mold type DI
This is for P (abbreviation for Dual In1ine Pack/@ge), and includes a group of many leads 2 and an IC element mounting part (
Three sets (hereinafter referred to as "islands") are continuously formed. As shown in FIG. 2, the lead frame 1 is usually plated with a noble metal such as gold or silver on the island 3 and the inner leading edge of the leads 2 to provide a package for an IC element. Generally, a precious metal is plated on the %PJr4J portion where the series leads 2 and islands 3) are formed by photo-etching or press punching a metal plate or metal strip. For example, a partial plating device that plated only the required area was developed by the Japanese government in 1973.
As described in Japanese Patent No. 72.47751, a material to be plated is held between a mask plate and a suppressing plate, which have holes that are completely transparent in the part to be plated, and a plating solution is injected into the holes, and at the same time, the material to be plated (cathode) is Electricity is passed between the electrode and the anode.

ところが、このような部分メッキをリードフレーム1に
適用、した場合、リードフレームは通常0.25簡程−
の厚さがある生め抑圧板とマスイ板で、挾持さ些たリー
ド2の側面付近顛若干の間豐を生じ否ことが避けやれず
、この間隙にメッキ液が侵入する結果第3図に示すよう
にリード2の両側面に正常のメッキ境界線4からはみ出
したメッキ漏れ部5が生じてしまう。このメッキ漏れ部
5を有するリードフレームに第2図の破線6を外形とす
る樹脂モールドを施すと、上記メッキ漏れ部5は樹脂と
外界との境界付近に達することになり、外界の湿度の影
響でリード間にエレクトロマイグレーンヨンが起きて短
絡するに至る。このマイグレーションは銀の場合特に顕
著である。メッキ境界線4と樹脂モールド外形線6との
距離が光分離れていれば多少のメッキ湿れ部5の存在は
あまり問題Kfiらないが、IC素子の集積度向上に伴
なってアイランド3が太きCI、樹脂モールド外形を一
定限度に抑えようとすればこの距離は小さくなり、メッ
キ漏れ部5の存在は許容されなくなる。例えば、第2図
の破線6の長さ方向の寸法が6.35 mm、貴金属メ
ッキ領域の長さ方向の寸法が6躯であると、両側におけ
るギャップは9.175mの如く狭小のものとなる。
However, when such partial plating is applied to lead frame 1, the lead frame usually has a thickness of 0.25 mm.
Due to the thickness of the pressing plate and the massaging plate, it is unavoidable that some gap will be generated near the sides of the small lead 2 being held, and as a result, the plating solution will enter this gap, as shown in Figure 3. As a result, plating leakage portions 5 protruding from the normal plating boundary line 4 are formed on both sides of the lead 2. When a resin mold having an outer shape indicated by the broken line 6 in FIG. 2 is applied to a lead frame having this plating leakage portion 5, the plating leakage portion 5 will reach the vicinity of the boundary between the resin and the outside world, and will be affected by the humidity of the outside world. Electromigration occurs between the leads, resulting in a short circuit. This migration is particularly noticeable in the case of silver. If the distance between the plating boundary line 4 and the resin mold outline line 6 is optically separated, the presence of some plating wet area 5 will not be much of a problem, but as the degree of integration of IC elements increases, the island 3 If an attempt is made to suppress the thick CI and the outer shape of the resin mold to a certain limit, this distance will become smaller, and the presence of the plating leakage portion 5 will no longer be tolerated. For example, if the lengthwise dimension of the broken line 6 in Figure 2 is 6.35 mm, and the lengthwise dimension of the precious metal plating area is 6, the gap on both sides will be as narrow as 9.175m. .

このようなメッキ漏れ部5を無くすにはり一ド2及びア
イランド3を形成する前に部分メッキを施せば良いと考
えられる。すなわち、第4図に示すように金属条7の両
縁部に位置決め用ビン孔8を設けておき、この金属条7
の中央部9に貴金属を部分メッキし、しかる後金携条7
をビン孔8を用いて位置決めしながらプレス打抜き加工
を施してリード2及びアイランド3を形成するのである
In order to eliminate such plating leakage portions 5, it is considered that partial plating should be performed before forming the boards 2 and islands 3. That is, as shown in FIG. 4, positioning holes 8 are provided at both edges of the metal strip 7.
The central part 9 of the metal plate is partially plated with precious metal, and then the gold carrying strip 7 is plated.
The lead 2 and the island 3 are formed by performing press punching while positioning using the pin hole 8.

ところがこの方法では最終的にリードフレームを形成し
てみ々いとメッキ位置が正確であるかどうか容易に判別
できない欠点がある。メッキ位置はビン孔8を用いれば
成る程度正確にはなるが、部分メッキ装置をプレス金型
はど精密に絹み立てることは困難なため、メッキ位置決
めピンとビン孔8とのクリアランスを大きくせざるを得
す、従ってこのビン孔8のみで正確さを期することは事
実上不可能である。このため通常の部分メッキ装置は他
の手段でメッキ位置を調節できるようにしている。例え
ば金属条を間欠的に送pながら連続的に部分メッキする
装置では幅方向の調節はガイドローラーで、長手方向の
調節は金属条の駆動装置の微調整で行なうようにしてい
る。しかしながらこの調節もメッキ後直ちに位置ズレを
確認できなければ有効に活用できない。メッキ後プレス
打抜き加工した後で初めてメッキ位置ズレを発見してか
らフィードバックするのでは大量のメツキネ良品を発生
させてしまうことになる。
However, this method has the disadvantage that it is not easy to determine whether the plating position is accurate after the lead frame is finally formed. The plating position can be made as accurate as possible by using the bottle hole 8, but it is difficult to accurately set the press mold of the partial plating device, so the clearance between the plating positioning pin and the bottle hole 8 has to be increased. Therefore, it is virtually impossible to ensure accuracy using only this bottle hole 8. For this reason, conventional partial plating apparatuses allow the plating position to be adjusted by other means. For example, in an apparatus for continuous partial plating while feeding a metal strip intermittently, adjustment in the width direction is performed by guide rollers, and adjustment in the longitudinal direction is performed by fine adjustment of a driving device for the metal strip. However, this adjustment cannot be used effectively unless positional deviations are confirmed immediately after plating. If a plating position shift is detected only after press punching after plating and then feedback is provided, a large number of defective products will be produced.

本発明は上記欠点を解消し、メッキ位置ズレをメッキ後
直ちに判別できるようにしたIC用リードフレームの製
造方法を提供するものである。この目的を達成するため
本発明は、金属条の両端部に位置決め用ビン孔と、上記
金属条の中央部にメッキ位置判別用貫通孔を形成し、上
記中央部に貴金属を部分メッキした後この金属条を上記
ビン孔を用いて位置合せしながらプレス打抜き加工を施
すことによシリードフレームを形成することを特徴とす
る。
The present invention eliminates the above-mentioned drawbacks and provides a method for manufacturing an IC lead frame in which misalignment in plating position can be determined immediately after plating. In order to achieve this object, the present invention forms positioning pin holes at both ends of the metal strip and a through hole for determining the plating position at the center of the metal strip, and after partially plating the center with precious metal, It is characterized in that the series lead frame is formed by press punching the metal strips while aligning them using the bin holes.

第5図は本発明の一実施例を説明するための図である。FIG. 5 is a diagram for explaining one embodiment of the present invention.

第5図において金属条7には両端部に位置決め用ビン孔
8と、中央部にチャンネル状の貫通孔10.11が設け
られている。これら貫通孔io、itは第1図における
リード2とアイランド3の間隙と一致するようにしであ
る。このような金属条7に第4図と同様に中央部9に貴
金属メッキを施せば第2図におけるリード2の先端にな
る部分及びアイランド3がメッキされることになる。位
置決め用ビン孔8と貫通孔10.11の形成はフォトエ
ツチングまたはプレス打抜き加工例れでもできる。中央
部9への貴金属メッキは、金属条7が短尺の場合は特公
昭49−24775号公報に記載されているようなバッ
チ式の部分メッキ装置で、長尺の場合は米国特許第3,
788,963号明細書に記載のような連続部分メッキ
装置で行なうことができる。何れの場合でもメッキ後の
金属条7を見れば貫通孔io、i1とメッキ位置の関係
を直ちに判別できるので、位置ズレが有ればすぐに金属
条7の位置を修正することができ、メッキ位置ズレによ
る不良品の発生を最小限にすることができる。部分メッ
キを施した金属条7はプレス打抜き加工に供し、ビン孔
8を用いて位置させながらリードフレームを形成すれば
、リードフレームの1群は外見上第2図に示すようにな
9、り一ド2の先端は第6図に示すように上面と端面に
はメッキ層を有し、両側面には全く貴金属メッキ層を有
しないリードフレームを得ることができる。
In FIG. 5, the metal strip 7 is provided with positioning holes 8 at both ends and a channel-shaped through hole 10.11 at the center. These through holes io and it are arranged to match the gap between the lead 2 and the island 3 in FIG. If the central portion 9 of such a metal strip 7 is plated with a precious metal in the same manner as shown in FIG. 4, the tip of the lead 2 and the island 3 in FIG. 2 will be plated. The positioning hole 8 and the through hole 10.11 can be formed by photo-etching or press punching. The precious metal plating on the central part 9 is carried out using a batch type partial plating apparatus as described in Japanese Patent Publication No. 49-24775 if the metal strip 7 is short, or using a batch-type partial plating apparatus as described in Japanese Patent Publication No. 49-24775 when the metal strip 7 is long;
It can be carried out in a continuous partial plating apparatus such as that described in US Pat. No. 788,963. In any case, if you look at the metal strip 7 after plating, you can immediately determine the relationship between the through holes io, i1 and the plating position, so if there is a positional deviation, you can immediately correct the position of the metal strip 7, and The occurrence of defective products due to misalignment can be minimized. The partially plated metal strip 7 is subjected to a press punching process, and if a lead frame is formed by positioning it using the bottle hole 8, the first group of lead frames will look like the one 9 shown in FIG. As shown in FIG. 6, the tip of the lead 2 has a plating layer on the upper surface and the end surface, and a lead frame having no precious metal plating layer on both side surfaces can be obtained.

メッキ位置判別用貫通孔の位置及び形状は第5図に示す
例に限定されるものではなく、リード2及びアイランド
3の形成に障害とならなければどのような位置及び形状
であ、ヤても差支えない。但し上記貫通孔の位置が中央
部のメッキ位置から離れ過ぎては位置ズレの判揃が困−
になるので、適当な位置にしなければならない。例えば
、幅方向詮よび/または長さ方向の中心線に対して線対
称の位置であっても良いし、メッキすべき領域の中心か
ら点対称の位置であっても良い。
The position and shape of the through hole for determining the plating position are not limited to the example shown in FIG. No problem. However, if the position of the through hole is too far from the center plating position, it will be difficult to align the misalignment.
Therefore, it must be placed in an appropriate position. For example, the position may be line symmetrical with respect to the center line in the width direction and/or length direction, or the position may be point symmetrical with respect to the center of the area to be plated.

上記説明はアイランド3のあるリードフレームについて
行なったが、アイランドの無いリードフレームの製造に
も本発明法は適用できる。この場合はアイランド30部
分をビン孔8と共に開孔させれば上記貫通孔をメッキ位
置ズレ判別に用いることができる。1だ、アイランド3
のあるリードフレームにおいて、アイランド30部分に
貴金属メッキを施さない場合もあるが、そのような場合
も本発明法に含゛上れることはいうまでもない。
Although the above explanation has been made regarding a lead frame with an island 3, the method of the present invention can also be applied to manufacturing a lead frame without an island. In this case, if the island 30 portion is opened along with the bottle hole 8, the through hole can be used for determining the plating position shift. 1, island 3
In some lead frames, the island 30 portion may not be plated with precious metal, and it goes without saying that such a case is also included in the method of the present invention.

本発明によれば、リード側面に貴金属メッキ層を有しな
いIC用リードフレームのメッキ位置を精度良く製造す
ることができ、材料歩留シを高めうると共にIC装置の
信頼性向上に大きく寄与することができる。
According to the present invention, the plating position of an IC lead frame that does not have a noble metal plating layer on the side surface of the lead can be manufactured with high precision, and the material yield can be increased and the reliability of the IC device can be significantly improved. I can do it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一般的なI’C用リードフレームの平面図。 第2図は第1図のリードフレームに貴金属メッキが施さ
れた状態の拡大平面図。 第3図は従来技術によるリード先端部分のメッキ漏れ部
分を示す斜視図。 第4図および第5図はそれぞれ金属条に設けたビン孔と
メッキ位置の関係、および本発明によるメッキ位置判別
用貫通孔の位置関係の具体例を示す説明図。 第′6.図は本発明によって形成されたメッキ層を有す
るリード先端の斜視図である。 1・・・リニドフ□、レーム;2・・・リード;3づイ
ランド:7・・・金属条;8・・・位置決め用ビン孔;
9・・・中央部:10,11・・・貫通孔。 特許出願人: 住友金属鉱山株式会社 代理人:弁理士海津保三 同   :  弁理士 平 山 −幸
FIG. 1 is a plan view of a general I'C lead frame. FIG. 2 is an enlarged plan view of the lead frame shown in FIG. 1 with precious metal plating applied thereto. FIG. 3 is a perspective view showing a plating leakage portion at the tip of a lead according to the prior art. FIGS. 4 and 5 are explanatory diagrams showing specific examples of the relationship between the via hole provided in the metal strip and the plating position, and the positional relationship of the through hole for determining the plating position according to the present invention, respectively. No. '6. The figure is a perspective view of a lead tip having a plating layer formed according to the present invention. 1... Linidoff □, frame; 2... Lead; 3 land: 7... Metal strip; 8... Positioning bottle hole;
9... Central part: 10, 11... Through hole. Patent applicant: Sumitomo Metal Mining Co., Ltd. Agent: Yasushi Kaizu, patent attorney: Yasuyuki Hirayama, patent attorney

Claims (1)

【特許請求の範囲】[Claims] 金属条の両縁部に位置決め用ビン孔と、上記金属条の中
央部にメッキ位置判別用貫通孔を形成し、上記中央部に
貴金属を部分メッキした憐この金属条を上記ピン孔を用
いて位置合せしながらプレス打抜き加工を施してリード
フレームを群成することを特徴とするIC用リードフレ
ームの製造方法。
A pin hole for positioning is formed on both edges of the metal strip, and a through hole for determining the plating position is formed in the center of the metal strip, and a metal strip partially plated with precious metal is formed in the center using the pin hole. A method for manufacturing an IC lead frame, which comprises forming lead frames into clusters by performing press punching while aligning the lead frames.
JP20865982A 1982-11-30 1982-11-30 Manufactue of lead frame for ic Granted JPS5999750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20865982A JPS5999750A (en) 1982-11-30 1982-11-30 Manufactue of lead frame for ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20865982A JPS5999750A (en) 1982-11-30 1982-11-30 Manufactue of lead frame for ic

Publications (2)

Publication Number Publication Date
JPS5999750A true JPS5999750A (en) 1984-06-08
JPH0141034B2 JPH0141034B2 (en) 1989-09-01

Family

ID=16559912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20865982A Granted JPS5999750A (en) 1982-11-30 1982-11-30 Manufactue of lead frame for ic

Country Status (1)

Country Link
JP (1) JPS5999750A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188952A (en) * 1983-04-11 1984-10-26 Shinko Electric Ind Co Ltd Manufacture of lead frame
US6047467A (en) * 1995-10-12 2000-04-11 Vlsi Technology, Inc. Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188952A (en) * 1983-04-11 1984-10-26 Shinko Electric Ind Co Ltd Manufacture of lead frame
JPH0135503B2 (en) * 1983-04-11 1989-07-25 Shinko Elec Ind
US6047467A (en) * 1995-10-12 2000-04-11 Vlsi Technology, Inc. Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads

Also Published As

Publication number Publication date
JPH0141034B2 (en) 1989-09-01

Similar Documents

Publication Publication Date Title
US4259436A (en) Method of making a take-carrier for manufacturing IC elements
US5126818A (en) Semiconductor device
KR100202286B1 (en) Leadframe and method of manufacturing the same
JPS5999750A (en) Manufactue of lead frame for ic
US4587185A (en) Photomask for use in making a carrier tape
JPH06179088A (en) Method for working metal sheet and manufacture of lead frame
JPH0770663B2 (en) Multi-faced etching products
JP2524645B2 (en) Lead frame and manufacturing method thereof
JPH09148503A (en) Manufacture of lead frame
US20020182370A1 (en) Semiconductor packaging part and method producing the same
JP2503652B2 (en) Semiconductor integrated circuit device and its inspection method
JP3674238B2 (en) Lead frame manufacturing method
JPH02210854A (en) Lead frame for semiconductor device and manufacture thereof
JP2022006921A (en) Lead frame, manufacturing method thereof, and method of manufacturing lead frame package
JPS58182858A (en) Lead frame
JPH0821658B2 (en) Lead frame manufacturing method
JP2528765B2 (en) Lead frames for semiconductor devices
JPS605551A (en) Manufacture of lead frame
JPH10294410A (en) Semiconductor mounting parts and its manufacture
JP2001121490A (en) Method of manufacturing printed wiring board for surface mounted parts
JPH0661394A (en) Semiconductor device
JPH05315496A (en) Manufacture of lead frame
JPH03265163A (en) Manufacturing device for lead frame
JPS60100694A (en) Partial plating method
JPH0479358A (en) Lead frame for semiconductor device