JPS5963822A - 自己校正型クロック及びタイミング信号発生器 - Google Patents

自己校正型クロック及びタイミング信号発生器

Info

Publication number
JPS5963822A
JPS5963822A JP58153986A JP15398683A JPS5963822A JP S5963822 A JPS5963822 A JP S5963822A JP 58153986 A JP58153986 A JP 58153986A JP 15398683 A JP15398683 A JP 15398683A JP S5963822 A JPS5963822 A JP S5963822A
Authority
JP
Japan
Prior art keywords
delay
stage
stages
clock
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58153986A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0362052B2 (enExample
Inventor
アレン・ジ−・ベル
リチヤ−ド・エフ・ライオン
ガエタノ−・ボリエロ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23633220&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPS5963822(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Xerox Corp filed Critical Xerox Corp
Publication of JPS5963822A publication Critical patent/JPS5963822A/ja
Publication of JPH0362052B2 publication Critical patent/JPH0362052B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
JP58153986A 1982-08-30 1983-08-23 自己校正型クロック及びタイミング信号発生器 Granted JPS5963822A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/412,490 US4494021A (en) 1982-08-30 1982-08-30 Self-calibrated clock and timing signal generator for MOS/VLSI circuitry
US412490 1982-08-30

Publications (2)

Publication Number Publication Date
JPS5963822A true JPS5963822A (ja) 1984-04-11
JPH0362052B2 JPH0362052B2 (enExample) 1991-09-24

Family

ID=23633220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58153986A Granted JPS5963822A (ja) 1982-08-30 1983-08-23 自己校正型クロック及びタイミング信号発生器

Country Status (5)

Country Link
US (1) US4494021A (enExample)
EP (1) EP0103404B1 (enExample)
JP (1) JPS5963822A (enExample)
BR (1) BR8304643A (enExample)
DE (1) DE3377560D1 (enExample)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62294320A (ja) * 1986-06-13 1987-12-21 Sony Corp 論理回路
JPS63146613A (ja) * 1986-10-07 1988-06-18 ウエスタン、デジタル、コ−ポレ−ション 遅延回路
JPH02296410A (ja) * 1989-05-11 1990-12-07 Mitsubishi Electric Corp 遅延回路
JPH03241918A (ja) * 1990-02-20 1991-10-29 Nippon Telegr & Teleph Corp <Ntt> 信号発生器
JPH098617A (ja) * 1995-06-15 1997-01-10 Nec Corp ディレイ制御回路
JPH09292930A (ja) * 1996-04-25 1997-11-11 Nec Corp 信号伝達用タイミング調整装置
WO2000065717A1 (fr) * 1999-04-27 2000-11-02 Seiko Epson Corporation Circuit de generation d'horloge, convertisseur en serie/en parallele et convertisseur en serie/en parallele, et dispositif semi-conducteur
US6259293B1 (en) * 1999-06-15 2001-07-10 Mitsubishi Denki Kabushiki Kaisha Delay circuitry, clock generating circuitry, and phase synchronization circuitry
WO2002011284A1 (fr) * 2000-07-27 2002-02-07 Thine Electronics, Inc. Circuit integre a semi-conducteurs
DE10006927C2 (de) * 1999-06-15 2003-04-17 Mitsubishi Electric Corp Verzögerungsschaltung
JPWO2010035309A1 (ja) * 2008-09-24 2012-02-16 株式会社アドバンテスト 遅延回路およびそれを用いたタイミング発生器および試験装置

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US4691124A (en) * 1986-05-16 1987-09-01 Motorola, Inc. Self-compensating, maximum speed integrated circuit
US4710653A (en) * 1986-07-03 1987-12-01 Grumman Aerospace Corporation Edge detector circuit and oscillator using same
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US5359727A (en) * 1987-04-27 1994-10-25 Hitachi, Ltd. Clock generator using PLL and information processing system using the clock generator
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US4912342A (en) * 1988-05-05 1990-03-27 Altera Corporation Programmable logic device with array blocks with programmable clocking
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US5157277A (en) * 1990-12-28 1992-10-20 Compaq Computer Corporation Clock buffer with adjustable delay and fixed duty cycle output
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US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
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US5585754A (en) * 1993-04-02 1996-12-17 Nec Corporation Integrated digital circuit
US5281927A (en) * 1993-05-20 1994-01-25 Codex Corp. Circuit and method of controlling a VCO with capacitive loads
US5436938A (en) * 1993-08-19 1995-07-25 Northern Telecom Limited Phase error detector for a phase locked loop
FR2732839B1 (fr) * 1993-12-27 1997-09-05 Medin David L Auto-etalonneur d'oscillateur
WO1995022206A1 (en) * 1994-02-15 1995-08-17 Rambus, Inc. Delay-locked loop
US5539348A (en) * 1994-03-17 1996-07-23 Advanced Micro Devices, Inc. Precise delay line circuit with predetermined reset time limit
US5554946A (en) * 1994-04-08 1996-09-10 International Business Machines Corporation Timing signal generator
US5666079A (en) * 1994-05-06 1997-09-09 Plx Technology, Inc. Binary relative delay line
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US5600273A (en) * 1994-08-18 1997-02-04 Harris Corporation Constant delay logic circuits and methods
JPH08111675A (ja) * 1994-10-07 1996-04-30 Mitsubishi Denki Eng Kk 同期回路
US5548237A (en) * 1995-03-10 1996-08-20 International Business Machines Corporation Process tolerant delay circuit
JP3355894B2 (ja) * 1995-09-27 2002-12-09 安藤電気株式会社 可変遅延回路
US5744991A (en) 1995-10-16 1998-04-28 Altera Corporation System for distributing clocks using a delay lock loop in a programmable logic circuit
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US6124744A (en) * 1996-03-26 2000-09-26 Kabushiki Kaisha Toshiba Electronic circuit apparatus having circuits for effectively compensating for clock skew
US5801566A (en) * 1996-04-03 1998-09-01 Mitsubishi Electric Semiconductor Software Co., Ltd. System clock generating circuit for a semiconductor device
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JP3080007B2 (ja) * 1996-08-28 2000-08-21 日本電気株式会社 Ｐｌｌ回路
US6060929A (en) * 1996-09-20 2000-05-09 Konica Corporation Signal delay apparatus
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US6084933A (en) * 1997-11-17 2000-07-04 Advanced Micro Devices, Inc. Chip operating conditions compensated clock generation
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JP3452834B2 (ja) * 1999-05-27 2003-10-06 ローム株式会社 遅延回路
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62294320A (ja) * 1986-06-13 1987-12-21 Sony Corp 論理回路
JPS63146613A (ja) * 1986-10-07 1988-06-18 ウエスタン、デジタル、コ−ポレ−ション 遅延回路
JPH02296410A (ja) * 1989-05-11 1990-12-07 Mitsubishi Electric Corp 遅延回路
JPH03241918A (ja) * 1990-02-20 1991-10-29 Nippon Telegr & Teleph Corp <Ntt> 信号発生器
JPH098617A (ja) * 1995-06-15 1997-01-10 Nec Corp ディレイ制御回路
JPH09292930A (ja) * 1996-04-25 1997-11-11 Nec Corp 信号伝達用タイミング調整装置
WO2000065717A1 (fr) * 1999-04-27 2000-11-02 Seiko Epson Corporation Circuit de generation d'horloge, convertisseur en serie/en parallele et convertisseur en serie/en parallele, et dispositif semi-conducteur
US6414528B1 (en) 1999-04-27 2002-07-02 Seiko Epson Corporation Clock generation circuit, serial/parallel conversion device and parallel/serial conversion device together with semiconductor device
US6259293B1 (en) * 1999-06-15 2001-07-10 Mitsubishi Denki Kabushiki Kaisha Delay circuitry, clock generating circuitry, and phase synchronization circuitry
DE10006927C2 (de) * 1999-06-15 2003-04-17 Mitsubishi Electric Corp Verzögerungsschaltung
WO2002011284A1 (fr) * 2000-07-27 2002-02-07 Thine Electronics, Inc. Circuit integre a semi-conducteurs
US7158441B2 (en) 2000-07-27 2007-01-02 Thine Electronics, Inc. Semiconductor integrated circuit
JPWO2010035309A1 (ja) * 2008-09-24 2012-02-16 株式会社アドバンテスト 遅延回路およびそれを用いたタイミング発生器および試験装置

Also Published As

Publication number Publication date
JPH0362052B2 (enExample) 1991-09-24
DE3377560D1 (en) 1988-09-01
EP0103404A3 (en) 1985-04-03
US4494021A (en) 1985-01-15
EP0103404B1 (en) 1988-07-27
BR8304643A (pt) 1984-04-10
EP0103404A2 (en) 1984-03-21

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