JPS5953947A - 入力デ−タ確認方式 - Google Patents

入力デ−タ確認方式

Info

Publication number
JPS5953947A
JPS5953947A JP57164339A JP16433982A JPS5953947A JP S5953947 A JPS5953947 A JP S5953947A JP 57164339 A JP57164339 A JP 57164339A JP 16433982 A JP16433982 A JP 16433982A JP S5953947 A JPS5953947 A JP S5953947A
Authority
JP
Japan
Prior art keywords
data
input
data processing
pattern
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57164339A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6318778B2 (enrdf_load_stackoverflow
Inventor
Hiroshi Hashimoto
博 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57164339A priority Critical patent/JPS5953947A/ja
Publication of JPS5953947A publication Critical patent/JPS5953947A/ja
Publication of JPS6318778B2 publication Critical patent/JPS6318778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
JP57164339A 1982-09-21 1982-09-21 入力デ−タ確認方式 Granted JPS5953947A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57164339A JPS5953947A (ja) 1982-09-21 1982-09-21 入力デ−タ確認方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57164339A JPS5953947A (ja) 1982-09-21 1982-09-21 入力デ−タ確認方式

Publications (2)

Publication Number Publication Date
JPS5953947A true JPS5953947A (ja) 1984-03-28
JPS6318778B2 JPS6318778B2 (enrdf_load_stackoverflow) 1988-04-20

Family

ID=15791288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57164339A Granted JPS5953947A (ja) 1982-09-21 1982-09-21 入力デ−タ確認方式

Country Status (1)

Country Link
JP (1) JPS5953947A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294747A (ja) * 1989-05-09 1990-12-05 Nec Corp 装置内監視方式

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48102543A (enrdf_load_stackoverflow) * 1972-04-04 1973-12-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48102543A (enrdf_load_stackoverflow) * 1972-04-04 1973-12-22

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294747A (ja) * 1989-05-09 1990-12-05 Nec Corp 装置内監視方式

Also Published As

Publication number Publication date
JPS6318778B2 (enrdf_load_stackoverflow) 1988-04-20

Similar Documents

Publication Publication Date Title
US5533126A (en) Key protection device for smart cards
EP1895431A1 (en) A method to embed protocol for system management bus implementation
KR880000232B1 (ko) 단말접속시스템
EP0106600B1 (en) Circuit for checking storage protection
WO1984001449A1 (en) Direct memory access interface arrangement
EP0041406B1 (en) Component identification in computer system
JPS5953947A (ja) 入力デ−タ確認方式
US4410988A (en) Out of cycle error correction apparatus
US4531215A (en) Validity checking arrangement for extended memory mapping of external devices
JPS5835284B2 (ja) デ−タバスチェック方式
JPH05250310A (ja) データ処理装置
JPH0444156A (ja) 転送データ生成装置
JPS62166637A (ja) 通信デ−タのコ−ド検出方式
JP2597484B2 (ja) データ転送方式
JPS6146541A (ja) デ−タ書き込み方式
JPS5936359B2 (ja) デ−タバツフア装置
JPS61134135A (ja) 転送制御方式
JPS59123913A (ja) Ｄｍａアクセス方式
JPS5810222A (ja) デ−タ転送方式
JPH0324601A (ja) 制御方法
JPS63696A (ja) キヤツシユドロアの制御方式
JPS63304356A (ja) Ｄｍａデ−タ転送の正常性検査方式
JPS6089263A (ja) メモリ内容保護方式
JPS63179644A (ja) 回線制御処理方式
JPH0340415B2 (enrdf_load_stackoverflow)