JPS5950561A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS5950561A
JPS5950561A JP57160999A JP16099982A JPS5950561A JP S5950561 A JPS5950561 A JP S5950561A JP 57160999 A JP57160999 A JP 57160999A JP 16099982 A JP16099982 A JP 16099982A JP S5950561 A JPS5950561 A JP S5950561A
Authority
JP
Japan
Prior art keywords
region
type
gate
semiconductor substrate
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57160999A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0430195B2 (enrdf_load_stackoverflow
Inventor
Shuji Ikeda
修二 池田
Koichi Nagasawa
幸一 長沢
Kotaro Nishimura
光太郎 西村
Yukio Sasaki
笹木　行雄
Akira Yamamoto
昌 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57160999A priority Critical patent/JPS5950561A/ja
Publication of JPS5950561A publication Critical patent/JPS5950561A/ja
Publication of JPH0430195B2 publication Critical patent/JPH0430195B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs

Landscapes

  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP57160999A 1982-09-17 1982-09-17 半導体集積回路装置 Granted JPS5950561A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57160999A JPS5950561A (ja) 1982-09-17 1982-09-17 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57160999A JPS5950561A (ja) 1982-09-17 1982-09-17 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS5950561A true JPS5950561A (ja) 1984-03-23
JPH0430195B2 JPH0430195B2 (enrdf_load_stackoverflow) 1992-05-21

Family

ID=15726643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57160999A Granted JPS5950561A (ja) 1982-09-17 1982-09-17 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS5950561A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6188555A (ja) * 1984-10-08 1986-05-06 Nec Corp 半導体メモリセル
JPS61212055A (ja) * 1985-03-18 1986-09-20 Oki Electric Ind Co Ltd 半導体記憶装置
US5264384A (en) * 1991-08-30 1993-11-23 Texas Instruments Incorporated Method of making a non-volatile memory cell

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153368A (ja) * 1982-03-09 1983-09-12 Toshiba Corp 絶縁ゲ−ト型電界効果トランジスタ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153368A (ja) * 1982-03-09 1983-09-12 Toshiba Corp 絶縁ゲ−ト型電界効果トランジスタ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6188555A (ja) * 1984-10-08 1986-05-06 Nec Corp 半導体メモリセル
JPS61212055A (ja) * 1985-03-18 1986-09-20 Oki Electric Ind Co Ltd 半導体記憶装置
US5264384A (en) * 1991-08-30 1993-11-23 Texas Instruments Incorporated Method of making a non-volatile memory cell

Also Published As

Publication number Publication date
JPH0430195B2 (enrdf_load_stackoverflow) 1992-05-21

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