JPS59221752A - エラ−検査・診断装置 - Google Patents
エラ−検査・診断装置Info
- Publication number
- JPS59221752A JPS59221752A JP59075914A JP7591484A JPS59221752A JP S59221752 A JPS59221752 A JP S59221752A JP 59075914 A JP59075914 A JP 59075914A JP 7591484 A JP7591484 A JP 7591484A JP S59221752 A JPS59221752 A JP S59221752A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- test
- maintenance
- flip
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP83105172A EP0126785B1 (de) | 1983-05-25 | 1983-05-25 | Prüf- und Diagnoseeinrichtung für Digitalrechner |
| EP831051727 | 1983-05-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59221752A true JPS59221752A (ja) | 1984-12-13 |
| JPH0223890B2 JPH0223890B2 (enExample) | 1990-05-25 |
Family
ID=8190487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59075914A Granted JPS59221752A (ja) | 1983-05-25 | 1984-04-17 | エラ−検査・診断装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4604746A (enExample) |
| EP (1) | EP0126785B1 (enExample) |
| JP (1) | JPS59221752A (enExample) |
| DE (1) | DE3379354D1 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3587621T2 (de) * | 1984-05-28 | 1994-03-24 | Advantest Corp | Logikanalysator. |
| JPH0668732B2 (ja) * | 1984-11-21 | 1994-08-31 | 株式会社日立製作所 | 情報処理装置のスキヤン方式 |
| JPH0670764B2 (ja) * | 1985-03-06 | 1994-09-07 | 株式会社日立製作所 | シ−ケンス制御装置 |
| DE3605431A1 (de) * | 1986-02-20 | 1987-08-27 | Vdo Schindling | Pruefbares elektronisches geraet und verfahren zum pruefen eines solchen geraets |
| US5247521A (en) * | 1986-04-23 | 1993-09-21 | Hitachi, Ltd. | Data processor |
| JPH0821028B2 (ja) * | 1986-04-23 | 1996-03-04 | 株式会社日立製作所 | デ−タ処理装置 |
| US5146605A (en) * | 1987-11-12 | 1992-09-08 | International Business Machines Corporation | Direct control facility for multiprocessor network |
| JP2996440B2 (ja) * | 1988-03-18 | 1999-12-27 | 富士通株式会社 | データ処理システムの診断方式 |
| JPH01320544A (ja) * | 1988-06-22 | 1989-12-26 | Toshiba Corp | テスト容易化回路 |
| US4947395A (en) * | 1989-02-10 | 1990-08-07 | Ncr Corporation | Bus executed scan testing method and apparatus |
| US5423025A (en) * | 1992-09-29 | 1995-06-06 | Amdahl Corporation | Error handling mechanism for a controller having a plurality of servers |
| US5951703A (en) * | 1993-06-28 | 1999-09-14 | Tandem Computers Incorporated | System and method for performing improved pseudo-random testing of systems having multi driver buses |
| US5598421A (en) * | 1995-02-17 | 1997-01-28 | Unisys Corporation | Method and system for tracking the state of each one of multiple JTAG chains used in testing the logic of intergrated circuits |
| US6119246A (en) * | 1997-03-31 | 2000-09-12 | International Business Machines Corporation | Error collection coordination for software-readable and non-software readable fault isolation registers in a computer system |
| US6065139A (en) * | 1997-03-31 | 2000-05-16 | International Business Machines Corporation | Method and system for surveillance of computer system operations |
| US6502208B1 (en) | 1997-03-31 | 2002-12-31 | International Business Machines Corporation | Method and system for check stop error handling |
| US5951686A (en) * | 1997-03-31 | 1999-09-14 | International Business Machines Corporation | Method and system for reboot recovery |
| US6557121B1 (en) | 1997-03-31 | 2003-04-29 | International Business Machines Corporation | Method and system for fault isolation for PCI bus errors |
| JP4064546B2 (ja) * | 1998-09-30 | 2008-03-19 | 株式会社アドバンテスト | 電気部品テストシステム |
| US20090083585A1 (en) * | 2007-09-21 | 2009-03-26 | Inventec Corporation | Method of pressure testing for peripheral component interconnect (pci) bus stage |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3582902A (en) * | 1968-12-30 | 1971-06-01 | Honeywell Inc | Data processing system having auxiliary register storage |
| US3651472A (en) * | 1970-03-04 | 1972-03-21 | Honeywell Inc | Multistate flip-flop element including a local memory for use in constructing a data processing system |
| US4023142A (en) * | 1975-04-14 | 1977-05-10 | International Business Machines Corporation | Common diagnostic bus for computer systems to enable testing concurrently with normal system operation |
| JPS5833576B2 (ja) * | 1977-03-14 | 1983-07-20 | 株式会社東芝 | 計算機システムの故障診断装置 |
| US4253183A (en) * | 1979-05-02 | 1981-02-24 | Ncr Corporation | Method and apparatus for diagnosing faults in a processor having a pipeline architecture |
| US4369511A (en) * | 1979-11-21 | 1983-01-18 | Nippon Telegraph & Telephone Public Corp. | Semiconductor memory test equipment |
| JPS57105897A (en) * | 1980-12-23 | 1982-07-01 | Fujitsu Ltd | Semiconductor storage device |
| US4412327A (en) * | 1981-02-25 | 1983-10-25 | Western Electric Company, Inc. | Test circuit for checking memory output state continuously during time window |
| US4429389A (en) * | 1981-05-26 | 1984-01-31 | Burroughs Corporation | Test pattern address generator |
| US4460997A (en) * | 1981-07-15 | 1984-07-17 | Pacific Western Systems Inc. | Memory tester having memory repair analysis capability |
| US4460999A (en) * | 1981-07-15 | 1984-07-17 | Pacific Western Systems, Inc. | Memory tester having memory repair analysis under pattern generator control |
| US4481627A (en) * | 1981-10-30 | 1984-11-06 | Honeywell Information Systems Inc. | Embedded memory testing method and apparatus |
| US4456995A (en) * | 1981-12-18 | 1984-06-26 | International Business Machines Corporation | Apparatus for high speed fault mapping of large memories |
| US4464747A (en) * | 1982-02-18 | 1984-08-07 | The Singer Company | High reliability memory |
| JPS58207152A (ja) * | 1982-05-28 | 1983-12-02 | Nec Corp | パイプライン演算装置テスト方式 |
| US4498172A (en) * | 1982-07-26 | 1985-02-05 | General Electric Company | System for polynomial division self-testing of digital networks |
| US4534028A (en) * | 1983-12-01 | 1985-08-06 | Siemens Corporate Research & Support, Inc. | Random testing using scan path technique |
-
1983
- 1983-05-25 EP EP83105172A patent/EP0126785B1/de not_active Expired
- 1983-05-25 DE DE8383105172T patent/DE3379354D1/de not_active Expired
-
1984
- 1984-04-17 JP JP59075914A patent/JPS59221752A/ja active Granted
- 1984-04-19 US US06/602,108 patent/US4604746A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0223890B2 (enExample) | 1990-05-25 |
| DE3379354D1 (en) | 1989-04-13 |
| EP0126785A1 (de) | 1984-12-05 |
| EP0126785B1 (de) | 1989-03-08 |
| US4604746A (en) | 1986-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59221752A (ja) | エラ−検査・診断装置 | |
| US4621363A (en) | Testing and diagnostic device for digital computers | |
| US4298980A (en) | LSI Circuitry conforming to level sensitive scan design (LSSD) rules and method of testing same | |
| EP0549602B1 (en) | Integrated circuit, system and method for fault insertion | |
| US5627842A (en) | Architecture for system-wide standardized intra-module and inter-module fault testing | |
| JP2590294B2 (ja) | 回路ボードテストシステムとテストベクトル供給システム及び生成方法 | |
| US4597042A (en) | Device for loading and reading strings of latches in a data processing system | |
| US3761695A (en) | Method of level sensitive testing a functional logic system | |
| US4074851A (en) | Method of level sensitive testing a functional logic system with embedded array | |
| US5056093A (en) | System scan path architecture | |
| CA2091087C (en) | Communications system to boundary-scan logic interface | |
| US4476431A (en) | Shift register latch circuit means contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques and utilized at least in part for check and test purposes | |
| US4340857A (en) | Device for testing digital circuits using built-in logic block observers (BILBO's) | |
| EP0419734B1 (en) | Method for testing a hierarchically organised integrated circuit device, and integrated circuit device suitable for being so tested | |
| US5450418A (en) | Pseudo master slave capture mechanism for scan elements | |
| US4485472A (en) | Testable interface circuit | |
| EP0040219B1 (en) | Data processor having common monitoring and memory loading and checking means | |
| EP0417905B1 (en) | System scan path architecture | |
| US6061284A (en) | Core test control | |
| US4682329A (en) | Test system providing testing sites for logic circuits | |
| DE3686073T2 (de) | Logischer schaltkreis. | |
| US5513187A (en) | Process for testing integrated circuits with at least one logic circuit and testable integrated circuit | |
| US20070168802A1 (en) | Semiconductor integrated circuit with test circuit | |
| Poirier | IEEE P1149. 5 to 1149.1 data and protocol conversion | |
| JPS62113075A (ja) | Lsi試験システム |