JPS59191742U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59191742U
JPS59191742U JP8619783U JP8619783U JPS59191742U JP S59191742 U JPS59191742 U JP S59191742U JP 8619783 U JP8619783 U JP 8619783U JP 8619783 U JP8619783 U JP 8619783U JP S59191742 U JPS59191742 U JP S59191742U
Authority
JP
Japan
Prior art keywords
semiconductor element
lead
connecting part
semiconductor equipment
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8619783U
Other languages
English (en)
Inventor
小関　隆之
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP8619783U priority Critical patent/JPS59191742U/ja
Publication of JPS59191742U publication Critical patent/JPS59191742U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来例の横断面図、第２図は第１図の側断面図
、第３図は本案の一実施例を示す横断面図、第４図は第
３図の側断面図である。 図中、１は基板、２はリード、２１〜２３はリード片、
３は連結部、４は半導体素子、６は金属細線、７は樹脂
材である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板に半導体素子を固定すると共に、半導体素子の電極
    と一端が半導体素子の近傍に位置するように配置された
    複数のリード片よりなるリードとを金属細線にて接続し
    、かつ半導体素子を含む主要部分を樹脂材にてモールド
    被覆したものにおいて、上記リードのうち、特定のリー
    ・ド片を基板に連結部を介して一体化すると共に、連結
    部を、それと基板とのなす角度θが９０°未満になるよ
    うに屈曲したことを特徴とする半導体装置。
JP8619783U 1983-06-06 1983-06-06 半導体装置 Pending JPS59191742U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8619783U JPS59191742U (ja) 1983-06-06 1983-06-06 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8619783U JPS59191742U (ja) 1983-06-06 1983-06-06 半導体装置

Publications (1)

Publication Number Publication Date
JPS59191742U true JPS59191742U (ja) 1984-12-19

Family

ID=30216138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8619783U Pending JPS59191742U (ja) 1983-06-06 1983-06-06 半導体装置

Country Status (1)

Country Link
JP (1) JPS59191742U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077211A (ja) * 2009-09-30 2011-04-14 Shindengen Electric Mfg Co Ltd 半導体パッケージ

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4985961A (ja) * 1972-12-22 1974-08-17
JPS5124864B1 (ja) * 1970-06-29 1976-07-27
JPS5279774A (en) * 1975-12-26 1977-07-05 Toshiba Corp Forming method for lead frame for resin sealing
JPS5636161B2 (ja) * 1973-11-20 1981-08-22

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5124864B1 (ja) * 1970-06-29 1976-07-27
JPS4985961A (ja) * 1972-12-22 1974-08-17
JPS5636161B2 (ja) * 1973-11-20 1981-08-22
JPS5279774A (en) * 1975-12-26 1977-07-05 Toshiba Corp Forming method for lead frame for resin sealing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077211A (ja) * 2009-09-30 2011-04-14 Shindengen Electric Mfg Co Ltd 半導体パッケージ

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