JPS59155748U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59155748U
JPS59155748U JP5103183U JP5103183U JPS59155748U JP S59155748 U JPS59155748 U JP S59155748U JP 5103183 U JP5103183 U JP 5103183U JP 5103183 U JP5103183 U JP 5103183U JP S59155748 U JPS59155748 U JP S59155748U
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor equipment
bent portion
leads
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5103183U
Other languages
English (en)
Inventor
柴田　啓司
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP5103183U priority Critical patent/JPS59155748U/ja
Publication of JPS59155748U publication Critical patent/JPS59155748U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来例の横断面図、第２図は第１図の側断面図
、第３図は本案の一実施例を示す横断面図、第４図は第
３図の側断面図である。 図中、１は基板部、２はリード、２□〜２３はリード片
、３はビード部、４は半導体素子、５は金属細線、６は
樹脂材である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板部に半導体素子を固定すると共に、半導体素子の電
    極と複数のリード片よりなるリードとを金属細線にて接
    続し、かつ半導体素子を含む主要部分を樹脂材にてモー
    ルド被覆したものにおいて、上記リードのうち、特定の
    リード片を基板部に対してほぼＬ形の屈曲部を介して一
    体化すると共に、屈曲部にビード部を形成したことを特
    徴とする半導体装置。
JP5103183U 1983-04-06 1983-04-06 半導体装置 Pending JPS59155748U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5103183U JPS59155748U (ja) 1983-04-06 1983-04-06 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5103183U JPS59155748U (ja) 1983-04-06 1983-04-06 半導体装置

Publications (1)

Publication Number Publication Date
JPS59155748U true JPS59155748U (ja) 1984-10-19

Family

ID=30181460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5103183U Pending JPS59155748U (ja) 1983-04-06 1983-04-06 半導体装置

Country Status (1)

Country Link
JP (1) JPS59155748U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52992A (en) * 1975-06-19 1977-01-06 Bayer Ag Method of making polychloroprene latex

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52992A (en) * 1975-06-19 1977-01-06 Bayer Ag Method of making polychloroprene latex

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