JPS58155836U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58155836U
JPS58155836U JP1982052302U JP5230282U JPS58155836U JP S58155836 U JPS58155836 U JP S58155836U JP 1982052302 U JP1982052302 U JP 1982052302U JP 5230282 U JP5230282 U JP 5230282U JP S58155836 U JPS58155836 U JP S58155836U
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor equipment
resin material
semiconductor
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982052302U
Other languages
English (en)
Inventor
明 山岸
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1982052302U priority Critical patent/JPS58155836U/ja
Publication of JPS58155836U publication Critical patent/JPS58155836U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来例の横断面図、第２図は第１図の正断面図
、第３図は本案の一実施例を示す横断面図、第４図は第
３図の正面図、第５図〜第６図は製造方法の説明図であ
って、第５図は放熱板とリードとの結合部材に半導体素
子をマウントした状態を示す平面図、第６図は樹脂モー
ルド状態を示す側断面図である。 図中、１は放熱板、２は半導体素子、３はリード、３１
〜３３はリード片、３１ａ＋３３ａは一端、４は金属細
線、５は樹脂材、５ａは外周面である。 第５図 第６図

Claims (1)

    【実用新案登録請求の範囲】
  1. 放熱板に半導体素子を固定すると共に、半導体素子の電
    極とリードとを金属細線にて接続し、かつ半導体素子を
    含む主要部分を樹脂材にてモールド被覆したものにおい
    て、上記リードの半導体素子側の一端を樹脂材の外周面
    に露出させたことを特徴とする半導体装置。
JP1982052302U 1982-04-09 1982-04-09 半導体装置 Pending JPS58155836U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982052302U JPS58155836U (ja) 1982-04-09 1982-04-09 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982052302U JPS58155836U (ja) 1982-04-09 1982-04-09 半導体装置

Publications (1)

Publication Number Publication Date
JPS58155836U true JPS58155836U (ja) 1983-10-18

Family

ID=30063010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982052302U Pending JPS58155836U (ja) 1982-04-09 1982-04-09 半導体装置

Country Status (1)

Country Link
JP (1) JPS58155836U (ja)

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