JPS5887339U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS5887339U JPS5887339U JP18252781U JP18252781U JPS5887339U JP S5887339 U JPS5887339 U JP S5887339U JP 18252781 U JP18252781 U JP 18252781U JP 18252781 U JP18252781 U JP 18252781U JP S5887339 U JPS5887339 U JP S5887339U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- resin material
- metal wire
- thin metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第１図は本案の一実施例を示す横断面図、第２図は第１
図の側断面図である。 図中、１は基板、２は半導体素子、３はリード、３１〜
３６はリード片、４は突出部、５は金属細線、６は樹脂
材である。
図の側断面図である。 図中、１は基板、２は半導体素子、３はリード、３１〜
３６はリード片、４は突出部、５は金属細線、６は樹脂
材である。
Claims (1)
- 基板に半導体素子を固定すると共１こ、半導体素子の電
極と一端が基板の近傍に位置するように配設されたリー
ドとを金属細線にて接続し、かつ半導体素子を含む主要
部分を樹脂材にてモールド被密したものにおいて、上記
リード樹脂材による被覆部分でかつ金属細線の接続経路
外に山形に突出する突出部を形成したことを特徴とする
半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18252781U JPS5887339U (ja) | 1981-12-08 | 1981-12-08 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18252781U JPS5887339U (ja) | 1981-12-08 | 1981-12-08 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5887339U true JPS5887339U (ja) | 1983-06-14 |
Family
ID=29980969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18252781U Pending JPS5887339U (ja) | 1981-12-08 | 1981-12-08 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5887339U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056372A (ja) * | 2008-08-29 | 2010-03-11 | Sanyo Electric Co Ltd | 樹脂封止型半導体装置とその製造方法 |
-
1981
- 1981-12-08 JP JP18252781U patent/JPS5887339U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010056372A (ja) * | 2008-08-29 | 2010-03-11 | Sanyo Electric Co Ltd | 樹脂封止型半導体装置とその製造方法 |
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