JPS5858346U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5858346U
JPS5858346U JP1981153727U JP15372781U JPS5858346U JP S5858346 U JPS5858346 U JP S5858346U JP 1981153727 U JP1981153727 U JP 1981153727U JP 15372781 U JP15372781 U JP 15372781U JP S5858346 U JPS5858346 U JP S5858346U
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor equipment
semiconductor
sides
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981153727U
Other languages
English (en)
Inventor
南部 哲司
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1981153727U priority Critical patent/JPS5858346U/ja
Publication of JPS5858346U publication Critical patent/JPS5858346U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図及び第2図は従来及び本案の一実施例を示す横断
面図である。1 図Φ、1は基板部、2は半導体素子、2a。 2bは辺、3はリード、3□〜36はリード片、4は金
属細線、5は!脂材、5aは樹脂モールド面である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基癖部に半導体素子を固定するち共に、ニ端が半導体素
    子の辺の近傍に位置するように配設されたリードと半導
    体素子の電極、と番金属細線にて接続し、かつ半導体素
    子を含む主要部分を樹脂材にてモールド被覆したものに
    おいて、上記半導体素子をほぼ象形に形成すると共に、
    この半導体素子を基板部に、半導体素子の隣接する2つ
    の辺がリードの導出側における樹脂モールド面に対して
    90″より小さい角度を有するように固定したことを特
    徴とする半導体装置。   □
JP1981153727U 1981-10-15 1981-10-15 半導体装置 Pending JPS5858346U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981153727U JPS5858346U (ja) 1981-10-15 1981-10-15 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981153727U JPS5858346U (ja) 1981-10-15 1981-10-15 半導体装置

Publications (1)

Publication Number Publication Date
JPS5858346U true JPS5858346U (ja) 1983-04-20

Family

ID=29946335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981153727U Pending JPS5858346U (ja) 1981-10-15 1981-10-15 半導体装置

Country Status (1)

Country Link
JP (1) JPS5858346U (ja)

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