JPS59191351A - 半導体装置における素子間分離酸化膜の形成方法 - Google Patents

半導体装置における素子間分離酸化膜の形成方法

Info

Publication number
JPS59191351A
JPS59191351A JP58066521A JP6652183A JPS59191351A JP S59191351 A JPS59191351 A JP S59191351A JP 58066521 A JP58066521 A JP 58066521A JP 6652183 A JP6652183 A JP 6652183A JP S59191351 A JPS59191351 A JP S59191351A
Authority
JP
Japan
Prior art keywords
oxide film
film
element isolation
etching
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58066521A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6339103B2 (enExample
Inventor
Yaichiro Watakabe
渡壁　弥一郎
Takayuki Matsukawa
隆行 松川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58066521A priority Critical patent/JPS59191351A/ja
Publication of JPS59191351A publication Critical patent/JPS59191351A/ja
Publication of JPS6339103B2 publication Critical patent/JPS6339103B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP58066521A 1983-04-13 1983-04-13 半導体装置における素子間分離酸化膜の形成方法 Granted JPS59191351A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58066521A JPS59191351A (ja) 1983-04-13 1983-04-13 半導体装置における素子間分離酸化膜の形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58066521A JPS59191351A (ja) 1983-04-13 1983-04-13 半導体装置における素子間分離酸化膜の形成方法

Publications (2)

Publication Number Publication Date
JPS59191351A true JPS59191351A (ja) 1984-10-30
JPS6339103B2 JPS6339103B2 (enExample) 1988-08-03

Family

ID=13318251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58066521A Granted JPS59191351A (ja) 1983-04-13 1983-04-13 半導体装置における素子間分離酸化膜の形成方法

Country Status (1)

Country Link
JP (1) JPS59191351A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4945069A (en) * 1988-12-16 1990-07-31 Texas Instruments, Incorporated Organic space holder for trench processing
US5387539A (en) * 1992-06-18 1995-02-07 Hyundai Electronics Industries Co., Ltd. Method of manufacturing trench isolation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4945069A (en) * 1988-12-16 1990-07-31 Texas Instruments, Incorporated Organic space holder for trench processing
US5387539A (en) * 1992-06-18 1995-02-07 Hyundai Electronics Industries Co., Ltd. Method of manufacturing trench isolation

Also Published As

Publication number Publication date
JPS6339103B2 (enExample) 1988-08-03

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