JPS59191351A - Method for formation of interelement isolation oxide film in semiconductor device - Google Patents

Method for formation of interelement isolation oxide film in semiconductor device

Info

Publication number
JPS59191351A
JPS59191351A JP6652183A JP6652183A JPS59191351A JP S59191351 A JPS59191351 A JP S59191351A JP 6652183 A JP6652183 A JP 6652183A JP 6652183 A JP6652183 A JP 6652183A JP S59191351 A JPS59191351 A JP S59191351A
Authority
JP
Japan
Prior art keywords
oxide film
film
element isolation
etching
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6652183A
Other languages
Japanese (ja)
Other versions
JPS6339103B2 (en
Inventor
Yaichiro Watakabe
渡壁 弥一郎
Takayuki Matsukawa
隆行 松川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6652183A priority Critical patent/JPS59191351A/en
Publication of JPS59191351A publication Critical patent/JPS59191351A/en
Publication of JPS6339103B2 publication Critical patent/JPS6339103B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To form a flat silicon oxide layer by a method wherein a recessed part is formed on an interelement isolation region by performing an etching, and a low temperature oxide film deposition and a thermal oxidation are performed thereon. CONSTITUTION:An SiO2 film 2a and an Si3N4 film 3a are formed on a silicon substrate 1, a recessed part 7 reaching the substrate 1 is formed on an interelement isolation region A by performing an etching, and the SiO2 film 2a and the Si3N4 film 3a are left on an active region B. Then, an isolation SiO2 film 8 is formed. Subsequently, a resist 9 for positive electron beam (EB) is applied, an electron beam is made to irradiate, a developing process is performed, and the EB resist layer 9a is left. Then, an etching is performed on the film 8 using the layer 9a as a mask. An SiO2 film 10 is then formed by performing thermal oxidation. As a result, a flat SiO2 isolation film having no bird's beak can be formed.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置における素子間分離酸化膜の形成
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of forming an isolation oxide film between elements in a semiconductor device.

〔従来技術〕[Prior art]

第1図(=)〜(c)は従来の素子間分離酸化膜の形成
方法を説明するためにその主要段階における状態を示す
断面図である。まず、第1図(a)に示すように、シリ
コン半導体基板ft1O上に酸化シリコン膜(2)を形
成し、更にその上に窒化シリコン膜(3)を形成した後
に、素子間分離領域Aに開口を有し活性化領域Bでは窒
化シリコン膜(3)を覆うレジストマスフ(4)を形成
する。そして、第1図(b)に示すようにレジストマス
ク(4)を介して窒化シリコン膜(3)にエツチングを
施して、素子分離領域Aにおける窒化シリコン膜(3)
を除去し、活性化領域Bに窒化シリコン膜(3a)を残
す。つづいて、レジストマスク(4)を除去して、窒化
シリコン膜(3a)をマスクとして選択酸化を施すと、
第1図(c)に示すように、素子間分離領域Aに厚い分
離酸化シリコン層(6)が形成される。酸化シリコン膜
(2)を用いている理由は、シリコン基板(1)と窒化
シリコン膜(3)との熱膨張係数の差によって生じるス
トレスを緩和するためである。上記第1図(0)の段階
における酸化は、例えば、高温の酸素雰囲中で長時間性
なわれる、窒化シリコン膜(3a)が存在する活性化領
域Bでは酸素の拡散が少なく、はとんどシリコン基板(
1)と反応せず、窒化シリコン膜(3a)のない素子間
分離(7イーivド)領域Aでは、シリコ7 基板[1
)は酸素と反応して分離酸化シリコン層(5)が形成さ
れるが、この分離酸化シリコン層(5)はシリコン基板
fi+の上面(活性化領域Bにおける)から尚該分離酸
化シリコン層(6)の厚さのA程度盛シ上がる。
FIGS. 1(a) to 1(c) are cross-sectional views showing the main stages of a conventional method for forming an element isolation oxide film. First, as shown in FIG. 1(a), a silicon oxide film (2) is formed on a silicon semiconductor substrate ft1O, and a silicon nitride film (3) is further formed on the silicon oxide film (3). A resist mask (4) having an opening and covering the silicon nitride film (3) in the active region B is formed. Then, as shown in FIG. 1(b), the silicon nitride film (3) is etched through the resist mask (4) to form a silicon nitride film (3) in the element isolation region A.
is removed, leaving the silicon nitride film (3a) in the active region B. Next, the resist mask (4) is removed and selective oxidation is performed using the silicon nitride film (3a) as a mask.
As shown in FIG. 1(c), a thick isolation silicon oxide layer (6) is formed in the element isolation region A. The reason why the silicon oxide film (2) is used is to alleviate the stress caused by the difference in thermal expansion coefficient between the silicon substrate (1) and the silicon nitride film (3). The oxidation at the stage shown in FIG. 1 (0) takes place for a long time in a high-temperature oxygen atmosphere, for example, in the active region B where the silicon nitride film (3a) is present, where there is little oxygen diffusion. Silicon substrate (
In the inter-element isolation (7e iv) region A which does not react with silicon nitride film (3a) and does not react with silicon nitride film (3a), the silicon 7 substrate [1
) reacts with oxygen to form an isolated silicon oxide layer (5), and this isolated silicon oxide layer (5) extends from the upper surface of the silicon substrate fi+ (in activated region B) to the isolated silicon oxide layer (6). ) to a thickness of about A.

そしてこれと同時に、窒化シリコン膜(3a)の端部の
下には分離酸化膜(6)がくい込んで、いわゆる「バー
ドビーク」と呼ばれる酸化膜の鳥のくちばし状の領域(
6)が形成される。
At the same time, the isolation oxide film (6) sinks under the edge of the silicon nitride film (3a), forming a bird's beak-shaped region of the oxide film called a "bird beak" (
6) is formed.

上述のような酸化シリコン膜(5)のくい込み、すなわ
ち、バードビーク(6)によって、例えば膜厚iμmの
分離酸化シリコン層を形成した場合、約0.5μm程夏
0くい込みが活性化領域Bの両側端がら生じる。これに
よって素子集積度が阻害される。
When an isolated silicon oxide layer with a film thickness of, for example, iμm is formed by the penetration of the silicon oxide film (5) as described above, that is, the bird's beak (6), the penetration of about 0.5μm occurs on both sides of the active region B. It arises from the edges. This hinders device integration.

〔発明の概要〕[Summary of the invention]

この発明は以上のような点に鑑みてなされたもので、エ
ツチングによって素子間分離領域に凹部・を形成し、低
温酸化膜デポジションと熱酸化とを組み合わせることに
よって、酸化シリコン層のくい込みが少なく、かつ、従
来に比して平坦な分離酸化シリコン層が形成できる方法
を提供するものである。
This invention was made in view of the above points, and by forming recesses in the element isolation region by etching and combining low-temperature oxide film deposition and thermal oxidation, it is possible to reduce the penetration of the silicon oxide layer. In addition, the present invention provides a method that can form an isolated silicon oxide layer that is planar compared to the conventional method.

〔発明の実施例〕[Embodiments of the invention]

第2図(a)〜(f)はこの発明の一実施例を説明する
ためにその主要段階における状態を示す断面図である。
FIGS. 2(a) to 2(f) are cross-sectional views showing the main stages of an embodiment of the present invention.

第1図の従来例と同等部分は同一符号で示す。Components equivalent to those of the conventional example shown in FIG. 1 are designated by the same reference numerals.

まず、第2図(a)に示すように、シリコン基板(tl
の上に下敷酸化シリコン(Sin2)膜(2)および窒
化シリコン(Eli3N4)膜(3)を順次形成し、素
子間分離領域Aにエツチングを施し、シリコン基板+1
1にまで所要深さに達する四部(7)を形成し、活性化
領域Bに5in2膜、(2a) 、 5t3N4膜(3
a)を残す。次に、第2図(b)に示すように、813
N4膜(3a)の上および素子間分離領域Aの凹部(7
)の内面を覆う分離5io2膜(8)をプラズマOVD
法などで形成する。つづいて、第2図(C)に示すよう
に、例えばポジ形電子ビーム用(gB)レジスト(9)
を5in2膜(8)上に凹部(7)の部分を埋めるよう
に塗布し、その上面全面に電子ビームを矢印で示すよう
に照射する。これに現像処理を施すと凹部(7)の部分
の底に近い部分は電子ビーム露光を受けなかったので、
第2図(d)に示すように、この部分だけにEBレジス
ト層(9a)が残る。
First, as shown in FIG. 2(a), a silicon substrate (tl
An underlying silicon oxide (Sin2) film (2) and silicon nitride (Eli3N4) film (3) are sequentially formed thereon, and the inter-element isolation region A is etched.
1, and a 5in2 film (2a) and a 5t3N4 film (3) are formed in the active region B.
Leave a). Next, as shown in FIG. 2(b), 813
The recess (7) on the N4 film (3a) and in the element isolation region A
) was plasma OVD applied to the separated 5io2 film (8) covering the inner surface of the
Formed by law etc. Next, as shown in FIG. 2(C), for example, a positive electron beam (gB) resist (9) is applied.
is applied onto the 5in2 film (8) so as to fill the concave portion (7), and the entire upper surface thereof is irradiated with an electron beam as shown by the arrow. When this was developed, the part near the bottom of the recess (7) was not exposed to the electron beam, so
As shown in FIG. 2(d), the EB resist layer (9a) remains only in this portion.

次に、このEBレジストNt (9a) yi:マスク
とじて5in2膜(8)にエツチングを施す。このエツ
チングは例えば47ツ化炭素(C!F4)と水素(H2
)との混合ガスを用いてプラズマエツチングする0この
と各活性化領域BのSiO□膜(8)を完全に除去する
ためにエツチングはオーバーぎみに行なうが、これによ
って第2図(e)に示すように、素子間分離領域Aの両
端部の51o2膜も除去されて、マスクとして用いたE
Bレジスト層(9a)の下にSiO□膜(8a)が残る
Next, the 5in2 film (8) is etched using this EB resist Nt (9a) yi: mask. For example, this etching is performed using carbon 47thride (C!F4) and hydrogen (H2).
). In order to completely remove the SiO□ film (8) in each activated region B, the etching is carried out slightly overly. As shown, the 51o2 film at both ends of the element isolation region A was also removed, and the E film used as a mask was removed.
The SiO□ film (8a) remains under the B resist layer (9a).

しかし、この素子間分離領域Aの両端部に生じる溝の幅
は/J%さく 5in2膜(8)の厚さが0.5μm程
度である場合には、そのデポジション方法およびその後
のエツチング条件にも依存するが0.2〜0.37an
程度になる。つづいて、第2図(f)に示すように熱酸
化によってこの溝部に5in2膜(10)を形成する。
However, the width of the groove formed at both ends of this inter-element isolation region A is /J%. It also depends, but it is 0.2 to 0.37 an
It will be about. Subsequently, as shown in FIG. 2(f), a 5in2 film (10) is formed in this groove by thermal oxidation.

溝の幅が0.2μmの場合、1100℃の温度の湿酸素
(Wet o2) 雰囲気中で5分間程度酸化すればよ
く、この程度の酸化ではバードビークは殆んど形成され
ず、平坦な分離5in2膜が形成される。
If the width of the groove is 0.2 μm, it is sufficient to oxidize for about 5 minutes in a wet oxygen (WetO2) atmosphere at a temperature of 1100°C. With this level of oxidation, almost no bird's beak is formed, and a flat separation of 5in2 is required. A film is formed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明では素子間分離領域にエ
ツチングによって凹部を形成し、その内面に低温で酸化
膜を形成し、上記凹部に対応して生じた酸化膜の凹部を
レジスト材で埋め、これをマスクとして上記酸化膜を除
去して素子間分離領域の両端部にシリコン基板の狭い幅
の露出部を形成しこれに短時間の熱酸化を施して酸化膜
で埋めて素子間分離酸化膜を形成するので、バードビー
クのない平坦な分離酸化膜が得られる。
As explained above, in the present invention, a recess is formed in the element isolation region by etching, an oxide film is formed on the inner surface of the recess at a low temperature, and the recess formed in the oxide film corresponding to the recess is filled with a resist material. Using this as a mask, the above oxide film is removed to form narrow exposed parts of the silicon substrate at both ends of the element isolation region, which are then thermally oxidized for a short time and filled with an oxide film to form an element isolation oxide film. As a result, a flat isolation oxide film without bird's beaks can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の素子間分離酸化膜の形成方法を説明する
ためにその主要段階における状態を示す断面図、第2図
はこの発明の一実施例を説明するためにその主要段階に
おける状態を示す断面図である。 図において、(1)はシリコン基板、(7)は凹部、(
8)。 (8a)はS10□膜(第1の酸化膜) 、(9) 、
 (9a)はEBレジスト材、(10)は5in2膜(
第2の酸化膜)である。 なお、図中同一符号は同一または相当部分を示す。 代理人  大 岩 増 雄 第1図 A A 〆 f
FIG. 1 is a sectional view showing the state at the main stages to explain a conventional method of forming an element isolation oxide film, and FIG. 2 shows the state at the main stages to explain an embodiment of the present invention. FIG. In the figure, (1) is a silicon substrate, (7) is a recess, (
8). (8a) is S10□ film (first oxide film), (9),
(9a) is EB resist material, (10) is 5in2 film (
second oxide film). Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 A A 〆 f

Claims (1)

【特許請求の範囲】[Claims] fi+  シリコン基板の素子間分離領域にエツチング
によって凹部を形成する第1の工程、上記凹部内面を含
めて上記シリコン基板上に低温にて第1の酸化膜を形成
する第2の工程、この第1の酸化膜の上にポジ形のレジ
スト材を塗布して上記凹部に対応して生じている上記第
1の酸化膜の凹部を上記レジスト材で実質的に埋める第
3の工程、上記レジスト材の全面に電子ビームまたはイ
オンビームを照射し現像処理を施して上記第1の酸化膜
の凹部に埋められ上記電子ビームまたはイオンビームの
照射が及ばなかった部分の上記レジスト材のみを残して
他の部分の上記レジスト材を除去する第4の工程、上記
残されたレジスト材をマスクとして上記素子間分離領域
の凹部内面の上記第1の酸化膜をエツチング除去し上記
マスク直下にのみ上記第1の酸化膜を残す第5の工程、
及び上記第5の工程のエツチングによって上記素子間分
離領域の凹部内に露出した上記シリコン基板の表面に熱
酸化によって第2の酸化膜を生せしめこの第2の酸化膜
を上記第5の工程で残された上記第1の酸化膜とで素子
間分離酸化膜を形成させる第6の工程を備えたことを特
徴とする半導体装置に′おける素子間分離酸化膜の形成
方法。
fi+ A first step of forming a recess by etching in an element isolation region of a silicon substrate; a second step of forming a first oxide film on the silicon substrate including the inner surface of the recess at a low temperature; a third step of applying a positive resist material onto the oxide film of the first oxide film to substantially fill in the recesses of the first oxide film corresponding to the recesses with the resist material; Irradiating the entire surface with an electron beam or ion beam and performing a development process, leaving only the resist material in the portions buried in the recesses of the first oxide film and not irradiated with the electron beam or ion beam, and leaving other portions. a fourth step of removing the resist material; using the remaining resist material as a mask, the first oxide film on the inner surface of the recess in the element isolation region is removed by etching, and the first oxide film is removed only directly under the mask; The fifth step of leaving a film,
A second oxide film is formed by thermal oxidation on the surface of the silicon substrate exposed in the recess of the element isolation region by the etching in the fifth step, and this second oxide film is formed in the fifth step. A method for forming an element isolation oxide film in a semiconductor device, comprising a sixth step of forming an element isolation oxide film with the remaining first oxide film.
JP6652183A 1983-04-13 1983-04-13 Method for formation of interelement isolation oxide film in semiconductor device Granted JPS59191351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6652183A JPS59191351A (en) 1983-04-13 1983-04-13 Method for formation of interelement isolation oxide film in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6652183A JPS59191351A (en) 1983-04-13 1983-04-13 Method for formation of interelement isolation oxide film in semiconductor device

Publications (2)

Publication Number Publication Date
JPS59191351A true JPS59191351A (en) 1984-10-30
JPS6339103B2 JPS6339103B2 (en) 1988-08-03

Family

ID=13318251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6652183A Granted JPS59191351A (en) 1983-04-13 1983-04-13 Method for formation of interelement isolation oxide film in semiconductor device

Country Status (1)

Country Link
JP (1) JPS59191351A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4945069A (en) * 1988-12-16 1990-07-31 Texas Instruments, Incorporated Organic space holder for trench processing
US5387539A (en) * 1992-06-18 1995-02-07 Hyundai Electronics Industries Co., Ltd. Method of manufacturing trench isolation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4945069A (en) * 1988-12-16 1990-07-31 Texas Instruments, Incorporated Organic space holder for trench processing
US5387539A (en) * 1992-06-18 1995-02-07 Hyundai Electronics Industries Co., Ltd. Method of manufacturing trench isolation

Also Published As

Publication number Publication date
JPS6339103B2 (en) 1988-08-03

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