JPS59188958A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS59188958A JPS59188958A JP6316783A JP6316783A JPS59188958A JP S59188958 A JPS59188958 A JP S59188958A JP 6316783 A JP6316783 A JP 6316783A JP 6316783 A JP6316783 A JP 6316783A JP S59188958 A JPS59188958 A JP S59188958A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive layer
- layer
- aperture
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 35
- 239000003990 capacitor Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体集積回路装置、特にアナログ−ディ
ジタル変換装置、特に容量素子を含む装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, particularly an analog-to-digital conversion device, and especially a device including a capacitive element.
一般的に、容量素子を用いる装置は、容量の装置内の比
精度を要求するもの多く、このため第１図Ａ（平面図）
および第１図Ｂ（第１図ＡのＡ−Ａ′部の断面図）に示
した様に、第１の電極１０３の外周に含まれる形状で第
２の電極１０５が形成されている。したがって第２の電
極１０５に対す゛る金属配線１０８の結線のための開口
１０７は、第１の電極１０３上に設ける必要があった。In general, many devices using capacitive elements require relative accuracy within the capacitive device, and for this reason, Fig. 1A (plan view)
As shown in FIG. 1B (a sectional view taken along line AA' in FIG. 1A), the second electrode 105 is formed in a shape included in the outer periphery of the first electrode 103. Therefore, the opening 107 for connecting the metal wiring 108 to the second electrode 105 had to be provided on the first electrode 103.
このため、例えば容量絶縁膜１０４をシリコン酸化膜で
形成し、第２の電極１０５を多結晶シリコン膜で形成し
た場合では、開口１０７形成に容量絶縁膜１０４が損傷
をうけ、しばしば、第１および第２の電極１０３，１０
５間で短絡するという事故が発生した。For this reason, when the capacitive insulating film 104 is formed of a silicon oxide film and the second electrode 105 is formed of a polycrystalline silicon film, for example, the capacitive insulating film 104 is damaged when the opening 107 is formed, and the first and second electrodes are often damaged. Second electrode 103, 10
An accident occurred in which a short circuit occurred between the two.
この発明の目的は、容量素子間の容量比精度が高く、か
つ信頼性の高い容量素子を提供することにある。An object of the present invention is to provide a capacitor element with high precision in the capacitance ratio between capacitor elements and with high reliability.
この発明による容量素子は、第１の電極となる導電層の
外周が第２の電極となる導電層を内部に含み、かつ、第
２の導電層の金属配線のための開口部において、第１の
導電層が除去され、該除去された領域が第２の導電層の
外周に含まれる形状をもつことを特徴としている。In the capacitive element according to the present invention, the outer periphery of the conductive layer serving as the first electrode includes the conductive layer serving as the second electrode, and the first The conductive layer is removed, and the removed region has a shape included in the outer periphery of the second conductive layer.
この発明によれば、第２の導電層への金属腕脚のための
開口部には、第１の導電層が存在しないため、開口形成
時の容量絶縁膜への損傷はなく、第１および第２導電層
間の短絡等の不都合を解消できる。まだ、第２導電層は
、第１導電層の外周に含まれ、第１導電層の除去領域は
、第２の導電層の外周に含まれるため、写真蝕刻時の目
合せずれ等に対しても、高い容量比精度を実現できる。According to this invention, since the first conductive layer is not present in the openings for the metal arms and legs to the second conductive layer, there is no damage to the capacitive insulating film when forming the openings, and the first and second conductive layers are not damaged. Inconveniences such as short circuits between the second conductive layers can be eliminated. However, the second conductive layer is included in the outer periphery of the first conductive layer, and the removed area of the first conductive layer is included in the outer periphery of the second conductive layer. Also, high capacitance ratio accuracy can be achieved.
次に図面を参考にしながら、この発明の一実施例につい
て説明する。菓２図Ａおよび第２図Ｂは、この発明によ
る容量素子のそれぞれ平面図および断面図（第２図Ａの
Ｂ−８７部）である。この実施例では、シリコン基板２
０１上に１．０μのフィールド酸化膜２０２が形成され
ており、この上に第１の電極となる０、５μの第１層多
結晶シリコン層２０３が形成されている。容量絶縁膜２
０４は、第１層多結晶シリコン層２０３を熱酸化するこ
とにより形成された５００Ａのシリコン酸化膜からなり
、さらに、第２の電極となる０、 ５μの第２層多結晶
シリコン層２０５が形成され、１．０μの層間絶縁酸化
膜２０６上を配線されるアルミニウム層２０８が開口２
０７を通して第２多結晶シリコン膜２０５と結線されて
いる。第１および第２多結晶シリコン膜２０３，２０５
には、リンが添加されており、層抵抗は３０Ω／口と容
量電極としては、十分低い値をもっている。Next, an embodiment of the present invention will be described with reference to the drawings. 2A and 2B are a plan view and a cross-sectional view (section B-87 in FIG. 2A), respectively, of a capacitive element according to the present invention. In this embodiment, the silicon substrate 2
A field oxide film 202 with a thickness of 1.0 μm is formed on the 0.01 μm, and a first polycrystalline silicon layer 203 with a thickness of 0.5 μm is formed thereon. Capacitive insulation film 2
04 consists of a 500A silicon oxide film formed by thermally oxidizing the first layer polycrystalline silicon layer 203, and furthermore, a 0.5 μm second layer polycrystalline silicon layer 205 is formed to become the second electrode. The aluminum layer 208 wired on the 1.0 μm interlayer insulating oxide film 206 is connected to the opening 2.
It is connected to the second polycrystalline silicon film 205 through 07. First and second polycrystalline silicon films 203, 205
Phosphorus is added to the layer, and the layer resistance is 30Ω/hole, which is sufficiently low for a capacitive electrode.
この発明によれば、開口２０７を形成する領域では、第
１層多結晶シリコン膜２０３には、２０３ ’で示す穴
が設けられているため、開口のためのエツチング等によ
り容量絶縁膜２０４が損傷をうけることが全くない。According to this invention, in the region where the opening 207 is to be formed, the first layer polycrystalline silicon film 203 is provided with a hole indicated by 203', so that the capacitive insulating film 204 is damaged due to etching for the opening, etc. I never receive any.
このため、第１および第２層多結晶シリコン換間の短絡
等の装置の破損および信頼性の低下を抑えることができ
る。また、第２層多結晶シリコン膜２０５の外周は、全
て、第１層多結晶シリコン膜２０３上に存在し、かつ、
第１層多結晶シリコン膜２０３の除去領域２０３′の外
周は全て第２層多結晶シリコン膜２０５に含まれている
ため、写真蝕刻法の目合せ誤差おるいは、エツチング時
の寸法転写誤差等に対しても、容量素子間の高い比精度
の容量を実現できる。Therefore, damage to the device such as a short circuit between the first and second polycrystalline silicon layers and a decrease in reliability can be suppressed. Further, the entire outer periphery of the second layer polycrystalline silicon film 205 exists on the first layer polycrystalline silicon film 203, and
Since the entire outer periphery of the removed region 203' of the first layer polycrystalline silicon film 203 is included in the second layer polycrystalline silicon film 205, there may be alignment errors in photolithography or dimension transfer errors during etching. It is also possible to realize capacitance with high specific accuracy between capacitive elements.
第１図Ａおよび第１図Ｂは、従来の容量素子を示すそれ
ぞれ平面図および断面図である。第２図Ａおよび第２図
Ｂは、この発明による一実施例の容量素子を示すそれぞ
れ平面図および断面図である０
図中％ １０１，２０１は半導体（シリコン）基板、１
０２．２０２はフィールド酸化膜、１０３，２０３は第
１の（多結晶シリコン）導電層電極、 １０４，２０４
は容１：（シリコン酸化膜）絶縁層、１０５，２０５は
第２の（多結晶シリコン）導電層電極、１０６，２０６
は眉間絶縁（酸化）膜、１０７，２０７は金属配線のだ
めの開口、１０８，２０８は（アルミニウム）金属配線
、２０３’は第１電極２０３の除去領域である。FIG. 1A and FIG. 1B are a plan view and a cross-sectional view, respectively, showing a conventional capacitive element. 2A and 2B are a plan view and a cross-sectional view, respectively, showing a capacitive element according to an embodiment of the present invention.
02.202 is a field oxide film, 103, 203 is a first (polycrystalline silicon) conductive layer electrode, 104, 204
is capacity 1: (silicon oxide film) insulating layer, 105, 205 is second (polycrystalline silicon) conductive layer electrode, 106, 206
107 and 207 are the openings for the metal wiring, 108 and 208 are the (aluminum) metal wiring, and 203' is the region where the first electrode 203 is removed.
Claims (2)
とを電極とし、第１および第２の導電層間に介在する容
量絶縁−膜とからなる容量素子を用いた半導体集積回路
装置において、第１の導電層の外周が第２の導電層を内
部に含み、かつ第２の導電層の金属配線のだめの開口部
において、第１の導電層が除去され、除去された領域は
、第２の導電層の外周に含まれる形状をもつことを特徴
とする半導体集積回路装置。(1) A semiconductor integrated circuit using a capacitive element consisting of a first conductive layer and a second conductive layer located above the first conductive layer as electrodes, and a capacitive insulating film interposed between the first and second conductive layers. In the apparatus, the outer periphery of the first conductive layer includes the second conductive layer therein, and the first conductive layer is removed at the opening of the metal wiring reservoir of the second conductive layer, and the removed area is , a semiconductor integrated circuit device having a shape included in the outer periphery of the second conductive layer.
量絶縁膜がシリコン酸化膜で形成されていることを特徴
とする特許請求の範囲第（１）項言己載の半導体集積回
路装置。(2) A semiconductor integrated circuit according to claim (1), wherein the second conductive layer is formed of a polycrystalline silicon film, and the capacitive insulating film is formed of a silicon oxide film. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6316783A JPS59188958A (en) | 1983-04-11 | 1983-04-11 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6316783A JPS59188958A (en) | 1983-04-11 | 1983-04-11 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59188958A true JPS59188958A (en) | 1984-10-26 |
| JPH0230582B2 JPH0230582B2 (en) | 1990-07-06 |
Family
ID=13221415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6316783A Granted JPS59188958A (en) | 1983-04-11 | 1983-04-11 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59188958A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58163A (en) * | 1981-06-25 | 1983-01-05 | Seiko Epson Corp | Manufacture of capacitor |
-
1983
- 1983-04-11 JP JP6316783A patent/JPS59188958A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58163A (en) * | 1981-06-25 | 1983-01-05 | Seiko Epson Corp | Manufacture of capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0230582B2 (en) | 1990-07-06 |
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