JPH03138973A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve accuracy to capacitance by connecting a dummy electrode for decreasing the errors at the time of patterning of an upper electrode to a low impedance power source end. CONSTITUTION:A capacitance element is provided, which consists of an upper electrode, being arranged through a dielectric film on the first conductive film 1 as a lower electrode and consisting of the second conductive films 2-1 and 2-1, and dummy electrodes 2a-1-1a-10, adjoining the upper electrode and being connected to low impedance power source ends. Hereby, parasitic capacitance C1 and C2, since dummy electrodes are grounded, becomes the capacitance between the first polysilicon film 1 (the first conductive film) and the earth ends and between the second polysilicon films 2-1 and 2-2 (the second conductive film) and the earth ends, and ceases to contribute to it as the capacitance between terminals A and B, so it becomes possible to remove the errors by parasitic capacitance and improve ratio accuracy.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and in particular to semiconductor integrated circuits that are widely used in switched capacitor filters, A/D converters, D/A converters, etc. The present invention relates to a semiconductor integrated circuit having a capacitive element (hereinafter referred to as a two-layer polysilicon capacitive element) formed of a layered polysilicon film.

[Conventional technology]

Traditionally, switched capacitor filters, A/D, D
Two-layer polysilicon capacitive elements used in /A converters and the like are generally constructed by arranging a plurality of unit capacitive elements to form various capacitance values.

This is to improve the capacitance ratio accuracy in the manufacturing process by making the pattern shapes the same.

Further, in order to improve the accuracy of the capacitance ratio by the pattern shape, dummy electrodes are arranged equidistantly around the second polysilicon film which becomes the upper electrode of the unit capacitance element, as shown in the conventional example of FIG. FIG. 3(a) is a layout diagram showing a two-layer polysilicon capacitive element, and FIG. 3(b) is a schematic cross-sectional view of a semiconductor chip taken along the line l-2 in FIG. 3(a). It is. In FIG. 3(a), 1 is the first polysilicon film for the lower electrode of the capacitor, and is connected to the contact 3-3.
It is connected to the wiring 4-2 and to the terminal B. 2-1
．． 2-2 is a second polysilicon film for the upper electrode of the capacitor, and is connected to the wiring 4-1 and to the terminal A through contacts 3-1, 3-2. In this figure, one second polysilicon film 2-1, 2-2 for the upper electrode constitutes a unit capacitance co, and two of these are connected in parallel. Further, 2a-1 to 2a-10 are dummy electrodes made of a second polysilicon film, and are arranged at equal distances from each other around the second polysilicon film 2-1, 2-2 forming a unit capacitance. ing. With this configuration, the second polysilicon film constituting each unit capacitance element has polysilicon films of the same layer order arranged around it at equal distances, so that each second polysilicon film constituting a unit capacitance element has the same layer order as the second polysilicon film arranged around the second polysilicon film at an equal distance. It is possible to reduce the error in the unit capacity and improve the relative accuracy.

[Problem to be solved by the invention]

However, in the conventional semiconductor integrated circuit described above, an electrically floating dummy electrode is arranged around the upper electrode of the capacitive element, so that the electrode terminal AB of the capacitive element
The disadvantage is that parasitic capacitance is generated between the two. Figure 3 (b
), co is the second polysilicon film 2-1.2-2
It is a unit capacitance formed by , and is connected between terminals A and B. However, the dummy electrode 2a forms parasitic capacitances C and C2 between the first polysilicon film for the lower electrode and the second polysilicon film for the upper electrode, respectively. Since the dummy electrode is not connected to anything else, the capacitance between terminals A and B appears as a series capacitance of C1 and C2. Therefore, if C2<<CI and the total parasitic capacitance between the two second polysilicon films and the dummy electrode is 07, the capacitance CAB between terminals A and B is CAB:2 Co + CT - (1), and the error is This results in the generation of Ct, and also causes deterioration of the capacitance ratio accuracy. This error occurs when the thickness of the second polysilicon film is 500 nm, the etching width is 0.1 μm, and Co = 8.
When 5 f F, C work is about 0.48 f F, so
It is around 0.28% (capacity ratio accuracy of 0.1% or less is required).

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a lower electrode made of a first conductive film formed on an insulating film of a semiconductor substrate, and a second conductive film disposed on the first conductive film with a dielectric film interposed therebetween. It has a capacitive element consisting of an upper electrode and a dummy electrode arranged adjacent to the upper electrode and connected to a low impedance power supply terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram showing a first embodiment of the present invention, and the same parts as in FIG. 3 (a>) are given the same numbers.

The difference from FIG. 3(a) is that the second polysilicon films 2a-1 to 2a-10 of the dummy electrodes are the contacts 3-4...
It is connected to the ground terminal via wiring 4-3. With this configuration, the parasitic capacitances C8 and C2 shown in FIG. 3(b) are reduced by grounding the dummy electrodes.
The capacitance is between the first polysilicon film (first conductive film) and the ground end, and between the second polysilicon film (second conductive film) and the ground end,
It no longer contributes to the capacitance between terminals A and B. Therefore,
The capacitance CAB between terminals A and B becomes CAB=2Co, making it possible to eliminate errors due to parasitic capacitance.

FIG. 2 is a layout diagram showing a second embodiment of the present invention.

In this embodiment as well, the second polysilicon film for the dummy electrode is connected to the ground end as in the first embodiment. The difference is that the second polysilicon film 2-1 constitutes the unit capacitance.
．． ．． Wires 4-1a and 4 are connected to 2-2 through contacts, respectively.
-1b, connected to terminal A and terminal C, and connected to the second polysilicon film 2 for the upper electrode of the capacitor. A polysilicon film 2a-12 is arranged. Therefore, terminals A, B
The capacitance between CAB and the capacitance between A and C is CAB=
CQ, CAC=CO, and as in FIG. 1, it is possible to eliminate the influence of the parasitic capacitance between the second polysilicon 2-1 and the dummy electrode and between 2-1 and 2-2.

In the above explanation, the case where the dummy electrode is connected to the ground terminal has been explained, but it is clear that the same effect can be obtained as long as it is a low impedance power supply terminal, and the shapes of the dummy electrode and the unit capacitor may be arbitrary.

〔Effect of the invention〕

As explained above, the present invention eliminates the influence of parasitic capacitance by connecting the dummy electrode placed slantwise to the low impedance power supply terminal to reduce errors during patterning of the upper electrode, and provides a capacitor with high capacitance ratio accuracy. This has the effect of realizing a semiconductor integrated circuit having elements.

1... first polysilicon film for lower electrode of capacitive element,
2-1.2-2... Second polysilicon film for upper electrode of capacitive element, 2a-1 to 2a-13... Second polysilicon film for dummy electrode, 3-1 to 3-3 -= Contact, 4-1.4-1a, 4-1b4-2.4-3...
・Wiring, Co-...unit capacitance, C1C2...parasitic capacitance.

Claims (1)

[Claims] 1. A lower electrode consisting of a first conductive film formed on an insulating film of a semiconductor substrate, and a second conductive film disposed on the first conductive film with a dielectric film interposed therebetween. 1. A semiconductor integrated circuit comprising a capacitive element comprising an upper electrode and a dummy electrode arranged adjacent to the upper electrode and connected to a low impedance power supply terminal. 2. The semiconductor integrated circuit according to claim 1, wherein the low impedance power supply terminal is a ground terminal.