GB1162759A - Monolithic Integrated Circuit - Google Patents
Monolithic Integrated CircuitInfo
- Publication number
- GB1162759A GB1162759A GB07551/67A GB1755167A GB1162759A GB 1162759 A GB1162759 A GB 1162759A GB 07551/67 A GB07551/67 A GB 07551/67A GB 1755167 A GB1755167 A GB 1755167A GB 1162759 A GB1162759 A GB 1162759A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- layers
- conductor
- plating
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007747 plating Methods 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 abstract 4
- 239000004020 conductor Substances 0.000 abstract 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 abstract 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract 1
- NPXOKRUENSOPAO-UHFFFAOYSA-N Raney nickel Chemical compound [Al].[Ni] NPXOKRUENSOPAO-UHFFFAOYSA-N 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 abstract 1
- VYRNMWDESIRGOS-UHFFFAOYSA-N [Mo].[Au] Chemical compound [Mo].[Au] VYRNMWDESIRGOS-UHFFFAOYSA-N 0.000 abstract 1
- 239000004411 aluminium Substances 0.000 abstract 1
- -1 aluminiumsilicon Chemical compound 0.000 abstract 1
- UNQHSZOIUSRWHT-UHFFFAOYSA-N aluminum molybdenum Chemical compound [Al].[Mo] UNQHSZOIUSRWHT-UHFFFAOYSA-N 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000009713 electroplating Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 229910017604 nitric acid Inorganic materials 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 230000007704 transition Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
1,162,759. Printed circuits; integrated circuit eccentrics. MOTOROLA Inc. 17 April, 1967 [9 May, 1966], No. 17551/67. Headings H1K and H1R. A monolithic, integrated circuit assembly comprises a semi-conductor die 19 (Figs. 3 and 4) with deposited circuit patterns on one surface thereof interconnected with semi-conductor regions; for instance base 18, emitter 56, and collector 83 of a transistor 21 are connected to a first conductive layer 23. The semi-conductor die is first coated on one surface with an insulating layer 79 formed of an oxide of the semiconductor material (e.g. SiO 2 ) to passivate all junctions terminating at said surface. The layer 79 is masked and etched, by phototechniques, to expose contact areas of said regions. The conductor layers may be of aluminum, aluminium - nickel, aluminiumsilicon, aluminum - molybdenum or molybdenum-gold formed by evaporative plating or electro-plating and converted into circuit patterns by photo-etching techniques using phosphoric, acetic or nitric acid solution. Preferably the layers are formed by plating first with aluminium and then nickel. The first conductive layer 23 is formed on the layer 79 and conductive layers 23, 27, 29 have insulating films 84, 86 sandwiched between them and insulating film 91 as the outer layer of the sandwich. Interconnections between conductive layers e.g. at transition areas 67, 68, 73 (Fig. 3) are formed by etching the insulation to expose areas of the underlying conductor and plating the upper conductor layer thereover. Connecting pads 25 are also formed this way. Capacitors, e.g. C33 (Fig. 3) and (Fig. 2, not shown), are formed from parts of layers 23 and 27 as electrodes with the insulating film 84 as dielectric. Resistors, e.g. 53, are deposited by vacuum plating with an appropriate resistor metal. The .insulating layers 84, 86, 91 are preferably vapour plated glasses such as boroalumina silica deposited at atmospheric pressure and temperatures below 450 C. There may be 200 circuits each including 40 gates on 1. square inch of chip.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US54865266A | 1966-05-09 | 1966-05-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1162759A true GB1162759A (en) | 1969-08-27 |
Family
ID=24189791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB07551/67A Expired GB1162759A (en) | 1966-05-09 | 1967-04-17 | Monolithic Integrated Circuit |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE1614155A1 (en) |
| GB (1) | GB1162759A (en) |
| NL (1) | NL6706418A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2169446A (en) * | 1985-01-07 | 1986-07-09 | Motorola Inc | Integrated circuit multilevel metallization and method for making same |
| GB2197540A (en) * | 1986-11-12 | 1988-05-18 | Murata Manufacturing Co | Circuit substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3849872A (en) * | 1972-10-24 | 1974-11-26 | Ibm | Contacting integrated circuit chip terminal through the wafer kerf |
-
1967
- 1967-04-17 GB GB07551/67A patent/GB1162759A/en not_active Expired
- 1967-05-05 DE DE19671614155 patent/DE1614155A1/en active Pending
- 1967-05-08 NL NL6706418A patent/NL6706418A/xx unknown
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2169446A (en) * | 1985-01-07 | 1986-07-09 | Motorola Inc | Integrated circuit multilevel metallization and method for making same |
| GB2197540A (en) * | 1986-11-12 | 1988-05-18 | Murata Manufacturing Co | Circuit substrate |
| US4800459A (en) * | 1986-11-12 | 1989-01-24 | Murata Manufacturing Co., Ltd. | Circuit substrate having ceramic multilayer structure containing chip-like electronic components |
| GB2197540B (en) * | 1986-11-12 | 1991-04-17 | Murata Manufacturing Co | A circuit structure. |
Also Published As
| Publication number | Publication date |
|---|---|
| NL6706418A (en) | 1967-11-10 |
| DE1614155A1 (en) | 1970-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3138744A (en) | Miniaturized self-contained circuit modules and method of fabrication | |
| US3771219A (en) | Method for manufacturing semiconductor device | |
| US3426252A (en) | Semiconductive device including beam leads | |
| GB1137907A (en) | Improvements in or relating to multiple-chip integrated circuit assembly with interconnection structure | |
| GB1426539A (en) | Multiple chip integrated circuits and method of manufacturing the same | |
| US3354360A (en) | Integrated circuits with active elements isolated by insulating material | |
| US3877063A (en) | Metallization structure and process for semiconductor devices | |
| US3590479A (en) | Method for making ambient atmosphere isolated semiconductor devices | |
| US3838443A (en) | Microwave power transistor chip carrier | |
| US3567506A (en) | Method for providing a planar transistor with heat-dissipating top base and emitter contacts | |
| US3543102A (en) | Composite semiconductor device composed of a plurality of similar elements and means connecting together only those elements having substantially identical electrical characteristics | |
| US3475664A (en) | Ambient atmosphere isolated semiconductor devices | |
| US3371148A (en) | Semiconductor device package and method of assembly therefor | |
| GB1162759A (en) | Monolithic Integrated Circuit | |
| GB1179983A (en) | Method of Fabricating Semiconductor Devices. | |
| US3397447A (en) | Method of making semiconductor circuits | |
| US4173768A (en) | Contact for semiconductor devices | |
| US3447038A (en) | Method and apparatus for interconnecting microelectronic circuit wafers | |
| US3739239A (en) | Semiconductor device and method of manufacturing the device | |
| US3715631A (en) | Radio-frequency line | |
| RU2076475C1 (en) | Thin-structure | |
| JP2545107B2 (en) | Circuit board | |
| US3461548A (en) | Production of an electrical device | |
| GB1190554A (en) | Improvements in or relating to Electrical Circuit Structures. | |
| GB1263381A (en) | Metal contact and interconnection system for nonhermetic enclosed semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PLNP | Patent lapsed through nonpayment of renewal fees |