JPS59171100A - メモリ装置 - Google Patents

メモリ装置

Info

Publication number
JPS59171100A
JPS59171100A JP58252511A JP25251183A JPS59171100A JP S59171100 A JPS59171100 A JP S59171100A JP 58252511 A JP58252511 A JP 58252511A JP 25251183 A JP25251183 A JP 25251183A JP S59171100 A JPS59171100 A JP S59171100A
Authority
JP
Japan
Prior art keywords
address
output
memory
input
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58252511A
Other languages
English (en)
Japanese (ja)
Other versions
JPH048874B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
ジエ−ムス・エツチ・クライン
デビツド・エム・チヤステイン
ジエ−ムス・デイ−・ガリア
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPS59171100A publication Critical patent/JPS59171100A/ja
Publication of JPH048874B2 publication Critical patent/JPH048874B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Storage Device Security (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP58252511A 1983-01-03 1983-12-29 メモリ装置 Granted JPS59171100A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US06454938 US4597061B1 (en) 1983-01-03 1983-01-03 Memory system using pipleline circuitry for improved system
US528316 1983-08-31
US454938 1989-12-22

Publications (2)

Publication Number Publication Date
JPS59171100A true JPS59171100A (ja) 1984-09-27
JPH048874B2 JPH048874B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-02-18

Family

ID=23806693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58252511A Granted JPS59171100A (ja) 1983-01-03 1983-12-29 メモリ装置

Country Status (2)

Country Link
US (1) US4597061B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS59171100A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5251181A (en) * 1991-06-05 1993-10-05 Kabushiki Kaisha Toshiba Random access memory device and method of controlling same in pipe line page mode
JPH0811414A (ja) * 1995-06-22 1996-01-16 Ricoh Co Ltd 印刷機の排紙装置

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US4920477A (en) * 1987-04-20 1990-04-24 Multiflow Computer, Inc. Virtual address table look aside buffer miss recovery method and apparatus
US4845677A (en) * 1987-08-17 1989-07-04 International Business Machines Corporation Pipelined memory chip structure having improved cycle time
GB2232797B (en) * 1989-06-16 1993-12-08 Samsung Semiconductor Inc RAM based serial memory with pipelined look-ahead reading
US5157775A (en) * 1989-12-15 1992-10-20 Eastman Kodak Company Dual port, dual speed image memory access arrangement
JP3179788B2 (ja) * 1991-01-17 2001-06-25 三菱電機株式会社 半導体記憶装置
US5287476A (en) * 1991-06-07 1994-02-15 International Business Machines Corp. Personal computer system with storage controller controlling data transfer
JPH05266652A (ja) * 1992-03-23 1993-10-15 Hitachi Ltd パイプライン動作型メモリシステム
US6278633B1 (en) 1999-11-05 2001-08-21 Multi Level Memory Technology High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations
US6473844B1 (en) * 2000-04-29 2002-10-29 Hewlett-Packard Company System and method to protect vital memory space from non-malicious writes in a multi domain system
US8522253B1 (en) 2005-03-31 2013-08-27 Guillermo Rozas Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
CN101449256B (zh) 2006-04-12 2013-12-25 索夫特机械公司 对载明并行和依赖运算的指令矩阵进行处理的装置和方法
EP2523101B1 (en) 2006-11-14 2014-06-04 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
US10228949B2 (en) 2010-09-17 2019-03-12 Intel Corporation Single cycle multi-branch prediction including shadow cache for early far branch prediction
CN103635875B (zh) 2011-03-25 2018-02-16 英特尔公司 用于通过使用由可分区引擎实例化的虚拟核来支持代码块执行的存储器片段
CN103547993B (zh) 2011-03-25 2018-06-26 英特尔公司 通过使用由可分割引擎实例化的虚拟核来执行指令序列代码块
TWI518504B (zh) 2011-03-25 2016-01-21 軟體機器公司 使用可分割引擎實體化的虛擬核心以支援程式碼區塊執行的暫存器檔案節段
CN103649932B (zh) 2011-05-20 2017-09-26 英特尔公司 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
KR101639854B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 상호접속 구조
WO2013077875A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. An accelerated code optimizer for a multiengine microprocessor
CN108427574B (zh) 2011-11-22 2022-06-07 英特尔公司 微处理器加速的代码优化器
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9430410B2 (en) 2012-07-30 2016-08-30 Soft Machines, Inc. Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
CN105210040B (zh) 2013-03-15 2019-04-02 英特尔公司 用于执行分组成块的多线程指令的方法
CN105247484B (zh) 2013-03-15 2021-02-23 英特尔公司 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US12189460B2 (en) * 2021-07-06 2025-01-07 UPBEAT TECHNOLOGY Co., Ltd Error detection and correction method and circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57135489A (en) * 1981-02-16 1982-08-21 Nippon Telegr & Teleph Corp <Ntt> Storage device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330852A (en) * 1979-11-23 1982-05-18 Texas Instruments Incorporated Semiconductor read/write memory array having serial access

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57135489A (en) * 1981-02-16 1982-08-21 Nippon Telegr & Teleph Corp <Ntt> Storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5251181A (en) * 1991-06-05 1993-10-05 Kabushiki Kaisha Toshiba Random access memory device and method of controlling same in pipe line page mode
JPH0811414A (ja) * 1995-06-22 1996-01-16 Ricoh Co Ltd 印刷機の排紙装置

Also Published As

Publication number Publication date
JPH048874B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-02-18
US4597061A (en) 1986-06-24
US4597061B1 (en) 1998-06-09

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Legal Events

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