CN108427574B - 微处理器加速的代码优化器 - Google Patents

微处理器加速的代码优化器 Download PDF

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CN108427574B
CN108427574B CN201810449173.XA CN201810449173A CN108427574B CN 108427574 B CN108427574 B CN 108427574B CN 201810449173 A CN201810449173 A CN 201810449173A CN 108427574 B CN108427574 B CN 108427574B
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instructions
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CN108427574A (zh
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M·阿布达拉
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]

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Abstract

本发明涉及微处理器加速的代码优化器。一种用于加速微处理器的代码优化的方法。该方法包括使用指令提取部件来提取传入的微指令序列并且向解码部件传送所提取的宏指令用于解码成微指令。通过将微指令序列重排序成包括多个依赖代码组的优化的微指令序列来执行优化处理。向微处理器流水线输出优化的微指令序列用于执行。优化的微指令序列的副本存储到序列高速缓存中，用于在后续命中优化的微指令序列时的后续使用。

Description

微处理器加速的代码优化器
本发明专利申请是国际申请号为PCT/US2011/061957，国际申请日为2011年11月22日，进入中国国家阶段的申请号为201180076248.0，名称为“微处理器加速的代码优化器”的发明专利申请的分案申请。
有关申请的交叉引用
本申请与Mohammad A.Abdallah提交于2010年1月5日、名称为"APPARATUS ANDMETHOD FOR PROCESSING COMPLEX INSTRUCTION FORMATS IN A MULTITHREADEDARCHITECTURE SUPPORTING VARIOUS CONTEXT SWITCH MODES AND VIRTUALIZATIONSCHEMES"的共同未决、共同转让的美国专利申请第2010/0161948号有关，并且将其完全结合于此。
本申请与Mohammad A.Abdallah提交于2008年12月19日、名称为"APPARATUS ANDMETHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYING PARALLEL IN DEPENDENTOPERATIONS"的共同未决、共同转让的美国专利申请第2009/0113170号有关，并且将其完全结合于此。
本申请与Mohammad A.Abdallah提交于2010年9月17日、名称为"SINGLE CYCLEMULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCHPREDICTION"共同未决、共同转让的美国专利申请第61/384,198号有关，并且将其完全结合于此。
本申请与Mohammad A.Abdallah提交于2011年3月25日、名称为"EXECUTINGINSTRUCTION SEQUENCE CODE BLOCKS BY USING VIRTUAL CORES INSTANTIATED BYPARTITIONABLE ENGINES"的共同未决、共同转让的美国专利申请第61/467,944号有关，并且将其完全结合于此。
技术领域
本发明总体上涉及数字计算机系统、更具体地涉及一种用于选择包括指令序列的指令的系统和方法。
背景技术
要求处理器处置相互依赖的多个任务或者完全独立的多个任务。这样的处理器的内部状态通常由可以在每个特定程序执行瞬间保持不同值的寄存器构成。在每个程序执行瞬间，内部状态映像被称为处理器的架构状态。
在切换代码执行以运行另一函数(例如另一线程、进程或者程序)时，必须保存机器/处理器的状态，从而新函数可以利用内部寄存器以构建它的新状态。一旦终止新函数，然后可以丢弃它的状态，并且将恢复先前上下文的状态并且执行重建。这样的切换过程被称为上下文切换并且尤其对于运用大量(例如64、128、256个)寄存器和/或无序执行的现代架构通常包括数十或者数百个周期。
在线程认知硬件架构中，对于硬件通常支持用于有限数目的由硬件支持的线程的多个上下文状态。在这一情况下，硬件重复用于每个支持的线程的所有架构状态元件。这消除对于在执行新线程时的上下文切换的需要。然而这仍然具有多个缺点、即为在硬件中支持的每个附加线程重复所有架构状态元件(即寄存器)的面积、功率和复杂性。此外，如果软件线程数目超过显式支持的硬件线程的数目，则仍然必须执行上下文切换。
这随着在需要大量线程的精细粒度基础上需要并行而变得普遍。具有重复上下文状态硬件存储的硬件线程认知架构无助于非线程式软件代码而仅减少用于线程式软件的上下文切换数目。然而那些线程通常被构造用于谷粒平行性并且造成用于启动和同步的繁重软件开销从而让精细粒度并行、比如函数调用和循环并行执行而没有高效线程启动/自动生成。这样的描述的开销伴随有难以使用现有技术的用于非显式/易于并行化/线程化的软件代码的编译器或者用户并行化技术的这样的代码的自动并行化。
发明内容
在一个实施例中，将本发明实施为一种用于加速微处理器中的代码优化的方法。该方法包括使用指令提取部件来提取传入的宏指令序列并且向解码部件传送所提取的宏指令用于解码成微指令。通过将微指令序列重排序成包括多个依赖代码组的优化的微指令序列来执行优化处理。然后向微处理器流水线输出优化的微指令序列用于执行。优化的微指令序列的副本被存储在序列高速缓存中用于在后续命中优化的微指令序列时的后续使用。
前文为发明内容、因此必然地包含简化、概括和省略的细节；因而本领域技术人员将理解发明内容仅为示例而未旨在于以任何方式限制。仅如权利要求限定的本发明的其它方面、发明特征和优点将在以下阐述的非限制具体描述中变得清楚。
附图说明
在附图的各图中通过示例而非通过限制来举例说明本发明，并且在附图中，相似标号指代相似元素。
图1示出根据本发明的一个实施例的微处理器的分配/发布级的概况图。
图2示出对根据本发明的一个实施例的优化过程进行图示的概况图。
图3示出根据本发明的一个实施例的多步骤优化过程。
图4示出根据本发明的一个实施例的多步骤优化和指令移动过程。
图5示出根据本发明的一个实施例的示例硬件优化过程的步骤的流程图。
图6示出根据本发明的一个实施例的备选示例硬件优化过程的步骤的流程图。
图7示出对根据本发明的一个实施例的分配/发布级的CAM匹配硬件和优先级编码硬件的操作进行示出的图。
图8示出对根据本发明的一个实施例的在分支之前的优化的调度进行图示的图。
图9示出对根据本发明的一个实施例的在存储之前的优化的调度进行图示的图。
图10示出根据本发明的一个实施例的示例软件优化过程的图。
图11示出根据本发明的一个实施例的SIMD基于软件的优化过程的流程图。
图12示出根据本发明的一个实施例的示例SIMD基于软件的优化过程的操作步骤的流程图。
图13示出根据本发明的一个实施例的基于软件的依赖性广播过程。
图14示出对根据本发明的一个实施例如何使用指令的依赖性分组以构建依赖指令的可变有界组的进行示出的示例流程图。
图15示出对根据本发明的一个实施例的指令的分级调度进行描绘的流程图。
图16示出对根据本发明的一个实施例的三时隙依赖性指令组的分级调度进行描绘的流程图。
图17示出对根据本发明的一个实施例的三时隙依赖性指令组的分级移动窗口调度进行描绘的流程图。
图18示出根据本发明的一个实施例如何向多个计算引擎分配指令的可变大小的依赖链(例如可变有界组)。
图19示出对根据本发明的一个实施例的向调度队列的块分配和三时隙依赖性指令组的分级移动窗口调度进行描绘的流程图。
图20示出根据本发明的一个实施例如何在引擎上执行依赖代码块(例如依赖性组或者依赖性链)。
图21示出根据本发明的一个实施例的多个引擎及其部件的概况图，这些部件包括全局前端提取和调度器和寄存器文件、全局互连以及用于多核处理器的片段式存储器子系统。
图22示出根据本发明的一个实施例的多个分段、多个分段式公共分区调度器和互连以及进入分段的端口。
图23示出根据本发明的一个实施例的示例微处理器流水线的图。
具体实施方式
虽然已经与一个实施例结合来描述本发明，但是本发明未旨在于限于这里阐述的具体形式。恰好相反，它旨在于覆盖如可以在如所附权利要求限定的本发明的范围内合理包括的这样的备选、修改和等同。
在以下具体描述中，已经阐述许多具体细节、比如具体方法顺序、结构、单元和连接。然而将理解无需利用这些和其它具体细节以实现本发明的实施例。在其它境况中，已经省略或者尚未具体描述公知结构、单元或者连接以免不必要地模糊本描述。
在说明书内对“一个实施例”或者“实施例”的引用旨在于指示与该实施例结合描述的特定特征、结构或者特性包含于本发明的至少一个实施例中。在说明书内的各处出现短语“在一个实施例中”未必都指代相同实施例，并且分离或者备选实施例未与其它实施例互斥。另外，描述各种特征可以被一些实施例而未被其它实施例表现。相似地，描述各种要求可以对于一些实施例、但是并非其它实施例的要求。
在对计算机存储器内的数据位的操作的流程、步骤、逻辑块、处理和其它符号表示方面呈现以下具体描述的一些部分。这些描述和表示是在数据处理领域中的技术人员用来向本领域中的其他技术人员最有效传达他们的工作的实质的手段。这里并且通常设想流程、计算机执行的步骤、逻辑块、过程等是促成所需结果的自一致步骤或者指令序列。该步骤是需要物理操控物理量的步骤。这些量尽管未必但是通常采用计算机可读存储介质的电信号或磁信号的形式并且能够在计算机系统中被存储、传送、组合、比较和另外操作。已经证实主要出于普遍用法的原因而将这些信号称为位、值、单元、符号、字符、项、数等有时是方便的。
然而应当谨记这些和相似术语中的所有术语将与适当物理量关联并且仅为应用于这些量的方便标签。除非如从以下讨论中清楚的那样另有具体明示，理解贯穿本发明利用术语、比如“处理”或者“访问”或者“写入”或者“存储”或者“重复”等的讨论指代计算机系统或者相似电子计算设备的动作和过程，该计算机系统或者电子计算设备将在计算机系统的寄存器和存储器以及其它计算机可读介质内的表示为物理(电子)量的数据操控和变换成在计算机系统存储器或者寄存器或者其它这样的信息存储、传输或者显示设备内的相似地表示为物理量的其它数据。
在一个实施例中，将本发明实施为一种用于加速微处理器中的代码优化的方法。该方法包括使用指令提取部件来提取传入的微指令序列并且向解码部件传送所提取的宏指令用于解码成微指令。通过将微指令序列重排序成包括多个依赖代码组的优化的微指令序列来执行优化处理。该优化的微指令序列被输出至微处理器流水线用于执行。优化的微指令序列的副本被存储在序列高速缓存中用于在向优化的微指令序列后续命中时的后续使用。
图1示出根据本发明的一个实施例的微处理器100的分配/发出级的概况图。如图1中所示，微处理器100包括提取部件101、本机解码部件102以及指令调度和优化部件110和微处理器的其余流水线105。
在图1的实施例中，宏指令由提取部件101提取并且由本机解码部件102解码成本机微指令，该本机解码部件然后向微指令高速缓存121以及指令调度和优化器部件110提供该本机微指令。在一个实施例中，所提取的宏指令包括通过预测某些分支而组装的指令序列。
宏指令序列由本机解码部件102解码成结果微指令序列。这一微指令序列然后通过复用器103向指令调度和优化部件110传输。该指令调度和优化器部件通过例如通过对微指令序列的某些指令重排序来执行优化处理用于更高效执行而工作。这产生然后通过复用器104向其余流水线105(例如分配、派发、执行和引退级等)传送的优化的微指令序列。该优化的微指令序列造成指令的更快和更高效执行。
在一个实施例中，宏指令可以是来自高级指令集架构的指令，而微指令是低级机器指令。在另一实施例中，宏指令可以是来自多个不同指令集架构(例如与CISC相似、x86、与RISC相似、MIPS、SPARC、ARM、与虚拟相似、JAVA等)的客户指令，而微指令是低级别机器指令或者不同本机指令集架构的指令。相似地，在一个实施例中，宏指令可以是架构的本机指令，并且微指令可以是该相同架构的已经重排序和优化的本机微指令。例如X86宏指令和X86微代码化的微指令。
在一个实施例中，为了加速频繁遇到的代码(例如热代码)的执行性能，在微指令高速缓存121内高速缓存频繁遇到的微指令序列的副本，并且在序列高速缓存122内高速缓存频繁遇到的优化的微指令序列的副本。在代码被提取、解码、优化和执行时，可以通过描绘的驱逐和填充路径130根据序列高速缓存的大小来驱逐或者提取某些优化的微指令序列。这一驱逐和填充路径允许向微处理器的存储器分级(例如L1高速缓存、L2高速缓存、特殊可缓冲存储器范围等)和从微处理器的存储器分级传送优化的微指令序列。
应当指出在一个实施例中可以省略微指令高速缓存121。在这样的实施例中，通过在序列高速缓存122内存储优化的微指令序列来提供热代码的加速。例如通过省略微指令高速缓存121而节省的空间可以例如用来实现更大序列高速缓存122。
图2示出对根据本发明的一个实施例的优化过程进行图示的概况图。图2的左手侧示出如例如从本机解码部件102或者微指令高速缓存121接收的传入的微指令序列。在第一次接收这些指令时，它们未被优化。
优化过程的一个目的是对相互依赖的指令进行定位和标识并且将它们移入它们的相应依赖性组中，从而它们可以更高效执行。在一个实施例中，可以一起派发依赖指令组，从而它们可以更高效执行，因为它们的相应源和目的被一起分组用于本地。应当指出这一优化过程可以使用在无序处理器以及依序处理器二者中。例如在依序处理器中，指令被依序地派发。然而可以到处移动它们，从而如以上描述的那样在相应组中放置依赖指令，使得组然后可以独立执行。
例如传入指令包括加载、操作和存储。例如指令1包括如下操作，在该操作中将源寄存器(例如寄存器9和寄存器9)相加并且将结果存储在寄存器5中。因此，寄存器5是目的而寄存器9和寄存器5是源。以这一方式，16个指令的序列如图所述包括目的寄存器和源寄存器。
图2的实施例实施指令重排序以创建依赖性组，其中属于组的指令相互依赖。为了实现这一点，执行关于16个传入指令的加载和存储执行危险校验的算法。例如存储在无依赖性校验的情况下就不能移动过去更早的加载。存储不能传递更早存储。加载在无依赖性校验的情况下就不能传递更早加载。加载可以传递加载。指令可以通过使用重命名技术来传递在先路径预测的分支(例如动态构造的分支)。在非动态预测的分支的情况下，指令移动需要考虑分支的范围。以上规则中的每个规则可以通过添加虚拟依赖性来实施(例如通过向指令人为添加虚拟源或者目的以施行规则)。
仍然参照图2，如以上描述的那样，优化过程的目的是对依赖指令进行定位并且将它们移入公共依赖性组。这一过程必须根据危险校验算法来完成。优化算法寻找指令依赖性。指令依赖性还包括真实依赖性、输出依赖性和反依赖性。
算法通过首先寻找真实依赖性来开始。为了标识真实依赖性，比较16指令序列的每个目的与在16指令序列中更晚出现的其它后续源。真实依赖于更早指令的后续指令被标记“_1”以表明它们的真实依赖性。这在图2中由在16指令序列上从左向右进行的指令编号示出。例如考虑指令编号4，比较目的寄存器R3与后续指令的源，并且每个后续源被标记“_1”以指示该指令的真实依赖性。在这一情况下，指令6、指令7、指令11和指令15被标记“_1”。
算法然后寻找输出依赖性。为了标识输出依赖性，比较每个目的与其它后续指令的目的。并且对于16个指令中的每个指令，匹配的每个后续目的被标记“1_”(例如有时称为红色目的)。
算法然后寻找反依赖性。为了标识反依赖性，对于16个指令中的每个指令，比较每个源与更早指令的源以标识匹配。如果匹配出现，则在考虑之下的指令标记它本身为“1_”(例如有时称为红色指令)。
以这一方式，算法填充用于16个指令的序列的行和列的依赖性矩阵。依赖性矩阵包括标记，这些标记指示用于16个指令中的每个指令的不同依赖性类型。在一个实施例中，通过使用CAM匹配硬件和适当广播逻辑在一个周期中填充依赖性矩阵。例如目的可以通过其余指令向下广播以与后续指令的源比较(例如真实依赖性)以及与后续指令的目的比较(例如输出依赖性)，而目的可以通过先前指令向上广播以与在先指令的源比较(例如反依赖性)。
优化算法使用依赖性矩阵以选择将哪些指令一起移入公共依赖性组。希望真实相互依赖的指令被移向相同组。寄存器重命名用来消除反依赖性以允许移动那些反依赖指令。该移动根据以上描述的规则和危险校验来完成。例如存储在无依赖性校验的情况下就不能移动过去更早的加载。存储不能传递更早存储。加载在无依赖性校验的情况下就不能传递更早存储。加载可以穿递加载。指令可以通过使用重命名技术来传递在先路径预测的分支(例如动态构造的分支)。在非动态预测的分支的情况下，指令移动需要考虑分支的范围。注意该描述。
在一个实施例中，可以实施优先级编码器以确定哪些指令获得移动以与其它指令分组。优先级编码器将根据依赖性矩阵提供的信息工作。
图3和图4示出根据本发明的一个实施例的多步骤优化过程。在一个实施例中，优化过程是迭代的，因为在指令通过移动它们的依赖性列在第一传递中被移动之后，重填充并且再次检查依赖性矩阵寻找移动指令的新机会。在一个实施例中，重复这一依赖性矩阵填充过程三次。这在图4中被示出，该图示出已经被移动、然后再次被检查寻找移动其它指令的机会的指令。在16个指令中的每个指令的右手侧上的编号序列示出指令在过程开始时所在的组和指令在过程完成时所在的组而在它们之间有居间组编号。例如图4示出指令6如何初始地在组4中、但是被移动在组1中。
以这一方式，图2至图4图示根据本发明的一个实施例的优化算法的操作。应当指出虽然图2至图4图示分配/发布级，但是也可以在本地调度器/派发级中实施这一功能。
图5示出根据本发明的一个实施例的示例硬件优化过程500的步骤的流程图。如在图5中描绘的那样，流程图示出根据本发明的一个实施例的如在微处理器的分配/发布级中实施的优化过程的操作步骤。
过程500在步骤501中开始，在该步骤中使用指令提取部件(例如来自图1的提取部件20)来提取传入宏指令序列。如以上描述的那样，提取的指令包括通过预测某些指令分支而组装的序列。
在步骤502中，将提取的宏指令向解码部件传送用于解码成微指令。该宏指令序列根据分支预测而解码成微指令序列。在一个实施例中，微指令序列然后在微指令高速缓存中存储。
在步骤503中，然后通过将包括微指令的序列重排序成依赖性组对微指令序列执行优化处理。重排序由指令重排序部件(例如指令调度和优化器部件110)实施。在图2至图4中描述这一过程。
在步骤504中，优化的微指令序列是向微处理器流水线的输出用于执行。如以上描述的那样，将优化的微指令序列向机器的其余部分转发用于执行(例如其余流水线105)。
并且后续在步骤505中，将优化的微指令序列的副本在序列高速缓存中存储用于在向该序列后续命中时的后续使用。以这一方式，序列高速缓存实现在后续命中优化的微指令序列时访问那些序列、由此加速热代码。
图6示出根据本发明的一个实施例的备选示例硬件优化过程600的步骤的流程图。如在图6中描绘的那样，流程图示出根据本发明的一个备选实施例的如在微处理器的分配/发布级中实施的优化过程的操作步骤。
过程600在步骤601中开始，在该步骤中使用指令提取部件(例如来自图1的提取部件20)来提取传入宏指令序列。如以上描述的那样，提取的指令包括通过预测某些指令分支而组装的序列。
在步骤602中，将提取的宏指令向解码部件传送用于解码成微指令。将宏指令序列根据分支预测解码成微指令序列。在一个实施例中，微指令序列然后在微指令高速缓存中存储。
在步骤603中，将所解码的微指令在微指令序列高速缓存中存储成序列。根据基本块边界形成微指令高速缓存中的序列以开始。这些序列在这一点未被优化。
在步骤604中，然后通过将包括微指令的序列重排序成依赖性组对微指令序列进行优化处理。重排序由指令重排序部件(例如指令调度和优化器部件110)实施。在图2至图4中描述这一过程。
在步骤605中，优化的微指令序列是向微处理器流水线的输出用于执行。如以上描述的那样，将优化的微指令序列向机器的其余部分转发用于执行(例如其余流水线105)。
并且后续在步骤606中，将优化的微指令序列的副本在序列高速缓存中存储用于在向该序列后续命中时用于后续使用。以这一方式，序列高速缓存实现在后续命中优化的微指令序列时访问那些序列、由此加速热代码。
图7示出对根据本发明的一个实施例的分配/发布级的CAM匹配硬件和优先级编码硬件的操作进行示出的图。如在图7中描绘的那样，从左侧向CAM阵列中广播指令的目的。示出三个示例指令目的。更浅色阴影的CAM(例如绿色)用于真实依赖性匹配和输出依赖性匹配，因此将该目的向下广播。更深色阴影(例如蓝色)用于反依赖性匹配，因此将目的向上广播。这些匹配如以上描述的那样填充依赖性矩阵。在右侧上示出优先级编码器，并且它们通过扫描CAM行以发现第一匹配“_1”或者“1_”来工作。如以上在图2-图4的讨论中描述的那样，该过程可以实施为迭代。例如，如果“_1”被“1_”阻塞，则可以将该目的重命名和移动。
图8示出对根据本发明的一个实施例的在分支之前的优化的调度指令进行图示的图。如图8中所示，与传统准时编译器实例并排描绘硬件优化的示例。图8的左手侧示出原有未优化的代码，该代码包括偏置的未取得的分支“Branch C to L1”。图8的中间列示出传统准时编译器优化，其中将寄存器重命名并且将指令移动在分支之前。在这一示例中，准时编译器插入补偿代码以考虑分支偏置判决错误的那些场合(例如其中将分支实际取得而不是未取得)。对照而言，图8的右列示出硬件展开的优化。在这一情况下，将寄存器重命名并且将指令移动在分支之前。然而应当指出未插入补偿代码。硬件保持对分支偏置判决是否为真的追踪。在错误预测的分支的情况下，硬件自动退回它的状态以便执行正确的指令序列。硬件优化器解决方案能够避免使用补偿代码，因为在那些情况下，在未命中预测分支时，硬件跳转至存储器中的原有代码并且从该原有代码执行正确序列而刷新未命中预测的指令序列。
图9示出对根据本发明的一个实施例的在存储之前的优化调度加载进行图示的图。如图9中所示，与传统准时编译器示例并排描绘硬件优化的示例。图9的左手侧示出包括存储“R3<-LD[R5]”的原有未优化的代码。图9的中间列示出传统准时编译器优化，其中将寄存器重命名并且将加载移动在存储之前。在这一示例中，准时编译器插入补偿代码以考虑加载指令的地址与存储指令的地址混淆的场合(例如其中将加载移动在存储之前是不适合的)。对照而言，图9的右列示出硬件展开的优化。在这一情况下，将寄存器重命名并且也将加载移动在存储之前。然而应当指出未插入补偿代码。在将加载移动在存储之前是错误的情况下，硬件自动退回它的状态以便执行正确的指令序列。硬件优化器解决方案能够避免使用补偿代码，因为在那些情况下，在未命中预测地址混淆校验分支的情况下，硬件跳转至存储器中的原有代码并且从该原有代码执行正确序列而刷新未命中预测的指令序列。在这一情况下，序列假设无混淆。应当指出在一个实施例中，在图9中图解的功能可以由图1的指令调度和优化器部件110实施。相似地，应当指出在一个实施例中，在图9中描绘的功能可以由以下在图10中描述的软件优化器1000实施。
此外，关于动态地展开的序列，应当指出指令可以通过使用重命名来传递在先路径预测的分支(例如动态构造的分支)。在非动态预测的分支的情况下，指令移动应当考虑分支的范围。可以在希望的程度上展开循环，并且可以跨越整个序列应用优化。例如这可以通过将跨越分支移动的指令的目的寄存器重命名来实施。这一特征的益处之一是无需补偿代码或者分支范围的广泛分析。这一特征因此大量加速和简化优化过程。
关于分支预测和指令序列的组装的附加信息可以在Mohammad A.Abdallah提交于2010年9月17日的、名称为"SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOWCACHE FOR EARLY FAR BRANCH PREDICTION"的、共同转让的美国专利申请第61/384,198号中发现，并且将其完全结合于此。
图10示出根据本发明的一个实施例的示例软件优化过程的图。在图10的实施例中，指令调度和优化器部件(例如图1的部件110)被基于软件的优化器1000替代。
在图10的实施例中，软件优化器1000执行由基于硬件的指令调度和优化器部件110执行的优化处理。软件优化器在存储器分级(例如L1、L2、系统存储器)中维护优化的序列的副本。这允许软件优化器维护与在序列高速缓存中存储的优化的序列的汇集比较的大得多的优化的序列的汇集。
应当指出软件优化器1000可以包括在存储器分级中驻留的代码作为向优化器的输入和从优化过程的输出二者。
应当指出在一个实施例中可以省略微指令高速缓存。在这样的实施例中，仅高速缓存优化的微指令序列。
图11示出根据本发明的一个实施例的SIMD基于软件的优化过程的流程图。图11的顶部示出基于软件的优化器如何检查输入指令序列的每个指令。图11示出SIMD比较如何可以用来匹配一个与许多(例如SIMD字节比较第一源“Src1”与所有第二源字节“Scr2”)。在一个实施例中，Src1包含任何指令的目的寄存器，并且Src2包含来自每个其它后续指令的一个源。对于每个目的完成与所有后续指令源匹配(例如真实依赖性校验)。这是指示用于指令的希望组的按对匹配。在每个目的与每个后续指令目的之间完成匹配(例如输出依赖性校验)。这是可以用重命名化解的阻塞匹配。在每个目的与每个在先指令源之间完成匹配(例如反依赖性匹配)。这是可以通过重命名化解的阻塞匹配。结果用来填充依赖性矩阵的行和列。
图12示出根据本发明的一个实施例的示例SIMD基于软件的优化过程1200的操作步骤的流程图。该过程1200在图9的流程图的上下文中描述。
在步骤1201中，通过使用基于软件的优化器实例化的存储器来访问输入指令序列。
在步骤1202中，使用SIMD指令用通过使用SIMD比较指令序列从输入指令序列抽取的依赖性信息来填充依赖性矩阵。
在步骤1203中，从右向左扫描矩阵的行寻找第一匹配(例如依赖性标记)。
在步骤1204中，分析第一匹配中的每个第一匹配以确定匹配的类型。
在步骤1205中，如果第一标记的匹配是阻塞依赖性，则对于这一目的完成重命名。
在步骤1206中，标识用于矩阵的每行的所有第一匹配并且将用于该匹配的对应列移向给定的依赖性组。
在步骤1207中，重复扫描过程若干次以对包括输入序列的指令重排序以产生优化的输出序列。
在步骤1208中，将优化的指令序列向微处理器的执行流水线输出用于执行。
在步骤1209中，将优化的输出序列存储在序列高速缓存中用于后续消耗(例如加速热代码)。
应当指出可以使用SIMD指令来串行完成软件优化。例如可以通过一次处理一个指令从而扫描指令的源和目的(例如从在序列中的更早指令到后续指令)来实施优化。软件使用SIMD指令以根据以上描述的优化算法和SIMD指令并行比较当前指令源和目的与在先指令源和目的(例如检测真实依赖性、输出依赖性和反依赖性)。
图13示出根据本发明的一个实施例的基于软件的依赖性广播过程。图13的实施例示出处理指令组而未以如以上描述的完全并行硬件实现方式为代价的示例软件调度过程的流程图。然而图13的实施例仍然可以使用SIMD以并行处理更小指令组。
图13的软件调度过程进行如下。首先，该过程初始化三个寄存器。该过程取得指令编号并且将它们加载到第一寄存器中。该过程然后取得目的寄存器编号并且将它们加载到第二寄存器中。该过程然后取得第一寄存器中的值并且根据第二寄存器中的位置编号将它们向第三结果寄存器中的位置广播。该过程然后在第二寄存器中从左向右改写，最左侧值将在广播去往结果寄存器中的相同位置的那些实例中改写右侧值。第三寄存器中的尚未写入的位置被绕过。这一信息用来填充依赖性矩阵。
图13的实施例也示出可以将输入指令序列处理为多组的方式。例如可以将16输入指令序列处理为第一组8个指令和第二组8个指令。利用第一组，将指令编号加载第一寄存器中，将指令目的编号加载到第二寄存器中，并且根据第二寄存器中的位置编号(例如组广播)将第一寄存器中的值向第三寄存器(例如结果寄存器)中的位置广播。第三寄存器中的尚未写入的位置被绕过。第三寄存器现在变成用于处理第二组的基础。例如来自组1的结果寄存器现在变成用于处理组二的结果寄存器。
利用第二组，将指令编号加载到第一寄存器中，将指令目的编号加载到第二寄存器中，并且根据第二寄存器中的位置编号将第一寄存器中的值向第三寄存器(例如结果寄存器)中的位置广播。在第三寄存器中的位置可以改写在处理第一组期间写入的结果。第三寄存器中的尚未写入的位置被绕过。以这一方式，第二组更新来自第一组的基础并且由此产生用于处理第三组的新基础并且以此类推。
在第二组中的指令可以继承在第一组的处理中生成的依赖性信息。应当指出无需处理整个第二组以更新结果寄存器中的依赖性。例如可以在第一组的处理中生成用于指令12的依赖性，然后处理第二组中的指令直至指令11。这更新结果寄存器为直至指令12的状态。在一个实施例中，掩码可以用来防止用于第二组的其余指令(例如指令12至16)的更新。为了确定用于指令12的依赖性，检查结果寄存器寻找R2和R5。将用指令1更新R5，并且将用指令11更新R2。应当指出在处理组2的全部的情况下将用指令15更新R2。
此外，应当指出可以相互独立处理第二组的所有指令(指令9-16)。在这样的情况下，第二组的指令仅依赖于第一组的结果寄存器。一旦根据第一组的处理更新结果寄存器，则第二组的指令可以并行处理。以这一方式，可以接连并行处理指令组。在一个实施例中，使用SIMD指令(例如SIMD广播指令)来处理每组、由此并行处理所述每组中的所有指令。
图14示出对根据本发明的一个实施例可以如何使用指令的依赖性分组以构建依赖指令的可变有界组进行示出的示例流程图。在图2至图4的描述中，组大小被约束，在那些情况下每组三个指令。图14示出如何可以将指令重排序成可变大小组，该可变大小组然后可以向多个计算引擎进行分配。例如图14示出4个引擎。由于组可以根据它们的特性而大小可变，所以引擎1可以被分配例如比引擎2更大的组。这可以例如在引擎2具有如下指令情况下出现，该指令未具体依赖于该组中的其它指令。
图15示出对根据本发明的一个实施例的指令的分级调度进行描绘的流程图。如以上描述的那样，指令的依赖性分组可以用来构建可变有界组。图15示出如下特征，其中各种依赖性级存在于依赖性组内。例如指令1未依赖于这一指令序列内的任何其它指令、因此使指令1成为L0依赖性级。然而指令4依赖于指令1、因此使指令4成为L1依赖性级。以这一方式，如图所示将指令序列的指令中的每个指令指派依赖性级。
每个指令的依赖性级由第二级分级调度器用来以确保资源可用于执行依赖指令这样的方式派发指令。例如在一个实施例中，将L0指令加载到第二级调度器1-4处理的指令队列中。加载L0指令使得它们在队列中的每个队列前面，加载L1指令使得它们在队列中的每个队列中跟随、L2指令跟随它们并且以此类推。这在图15中由从L0至Ln的依赖性级示出。调度器1-4的分级调度有利地利用在时间上局部和指令到指令依赖性以用最优方式做出调度判决。
以这一方式，本发明的实施例提示用于指令序列的指令的依赖性组时隙分配。例如为了实施无序微架构，指令序列的指令的派发是无序的。在一个实施例中，在每个周期上校验指令准备就绪。如果先前已经派发它依赖于的所有指令，则指令准备就绪。调度器结构通过校验那些依赖性来工作。在一个实施例中，调度器是统一的调度器，并且在统一的调度器结构中执行所有依赖性校验。在另一实施例中，跨越多个引擎的执行单元的派发队列分布调度器功能。因此，在一个实施例中，调度器是统一的，而在另一实施例中，调度器是分布的。利用这两种解决方案，每个周期按照派发指令的目的来校验每个指令源。
因此，图15示出如本发明的实施例执行的分级调度。如以上描述的那样，首先将指令分组以形成依赖性链(例如依赖性组)。这些依赖性链的形成可以通过软件或者硬件静态或者动态完成。一旦这些依赖性链已经形成，可以向引擎分布/派发它们。以这一方式，依赖性分组允许无序调度的有序形成的组。依赖性分组也向多个引擎(例如核或者线程)上分布整个依赖性组。依赖性分组也有助于如以上描述的分级调度，其中依赖指令在第一步骤中被分组、然后在第二步骤中被调度。
应当指出在图14-图19中图解的功能可以与用来对指令进行分组的任何方法(例如是否在硬件、软件等中实施分组功能)独立地工作。此外，图14-图19中所示依赖性分组可以包括独立组的矩阵，其中每组还包括依赖指令。此外，应当指出调度器也可以是引擎。在这样的实施例中，调度器1-4中的每个调度器可以被并入于它的相应引擎内(例如如图22中所示，其中每个分段包括公共分区调度器)。
图16示出对根据本发明的一个实施例的三时隙依赖性指令组的分级调度进行描绘的流程图。如以上描述的那样，指令的依赖性分组可以用来构建可变有界组。在这一实施例中，依赖性组包括三个时隙。图16示出甚至在三时隙依赖性组内的各种依赖性级。如以上描述的那样，指令1未依赖在这一指令序列内的任何其它指令、因此使指令1成为L0依赖性级。然而指令4依赖于指令1、因此使指令4成为L1依赖性级。以这一方式，如图所示将指令序列的指令中的每个指令指派依赖性级。
如以上描述的那样，每个指令的依赖性级由第二级分级调度器用来以确保资源可用于执行依赖指令这样的方式来派发指令。将L0指令加载到第二级调度器1-4处理的指令队列中。如图6中从L0至Ln的依赖性级所示，加载L0指令使得它们在队列中的每个队列前面，加载L1指令使得它们在队列中的每个指令中跟随、L2指令跟随它们并且以此类推。应当指出组编号四(例如从顶部起的第四组)即使它是分离组仍然在L2开始。这是因为指令7依赖指令4，指令4依赖指令1，由此向指令7给予L2依赖性。
以这一方式，图16示出如何在调度器1-4中的给定的调度器上一起调度每三个依赖指令。在第一级组后面调度第二级组，然后旋转该组。
图17示出对根据本发明的一个实施例的三时隙依赖性指令组的分级移动窗口调度进行描绘的流程图。在这一实施例中，经由统一的移动窗口调度器实施用于三时隙依赖性组的分级调度。移动窗口调度器处理队列中的指令以用确保资源可用于执行依赖指令这样的方式来派发指令。如以上描述的那样，向第二级调度器1-4处理的指令队列中加载L0指令。如图17中从L0至Ln的依赖性级所示，加载L0指令使得它们在队列中的每个队列前面，加载L1指令使得它们在队列中的每个队列中跟随，L2指令跟随它并且以此类推。移动窗口图示如何可以从队列中的每个队列派发L0指令，即使它们可以在一个队列而不是另一队列中。以这一方式，移动窗口调度器如图17中所示随着队列从左向右流动而派发指令。
图18示出根据本发明的一个实施例如何向多个计算引擎分配指令的可变大小依赖链(例如可变有界组)。
如图18中描绘的那样，处理器包括指令调度器部件10和多个引擎11-14。该指令调度器部件生成代码块和继承矢量以支持在它们的相应引擎上执行依赖代码块(例如可变有界组)。依赖代码块中的每个依赖代码块可以属于相同逻辑核/线程或者不同逻辑核/线程。指令调度器部件将处理依赖代码块以生成相应继承矢量。这些依赖代码块和相应继承矢量如图所示向特定引擎11-14分配。全局互联30支持跨越引擎11-14中的每个引擎的必需通信。应当指出如以上在图14的讨论中描述的用于指令的依赖性分组以构建依赖指令的可变有界组的功能由图18的实施例的指令调度器部件10实施。
图19示出对根据本发明的一个实施例的向调度队列的块分配和三时隙依赖性指令组的分级移动窗口调度进行描绘的流程图。如以上描述的那样，可以经由统一的移动窗口调度器实施用于三时隙依赖性组的分级调度。图19示出依赖性组如何变成向调度队列中加载的块。在图19的实施例中，可以在每个队列中加载两个独立组作为半块。这在图19的顶部被示出，其中组1形成向第一调度队列中加载的一个半块并且组4形成另一半块。
如以上描述的那样，移动窗口调度器处理队列中的指令以用确保资源可用于执行依赖指令这样的方式分派指令。图19的底部示出如何向第二级调度器处理的指令队列中加载L0指令。
图20示出根据本发明的一个实施例如何在引擎11-14上执行依赖代码块(例如依赖性组或者依赖性链)。如以上描述的那样，指令调度器部件生成代码块和继承矢量以支持在它们的相应引擎上执行依赖代码块(例如可变有界组、三时隙组等)。如以上在图19中描述的那样，图20还示出如何可以向每个引擎中加载两个独立组作为代码块。图20示出如何向引擎11-14派发这些代码块，其中依赖指令在每个引擎的堆叠(例如串联连接)的执行单元上执行。例如在图20的左上部上的第一依赖性组或者代码块中，向引擎11派发指令，其中按照它们的依赖性的顺序在执行单元上堆叠它们，从而在L1上面堆叠L0，在L2上进一步堆叠L1。在这样做时，L0的结果流向L1的执行单元，L1然后可以流向L2的执行。
以这一方式，图20中所示依赖性组可以包括独立组的矩阵，其中每组还包括依赖指令。组独立的益处是有能力并行派发和执行它们以及最小化对于跨越在引擎之间的互连的通信的需要这样的属性。此外，应当指出图11-14中所示执行单元可以包括CPU或者GPU。
根据本发明的实施例，应当理解指令根据它们的依赖性被抽象化成依赖性组或者块或者指令矩阵。根据指令的依赖性对它们进行分组有助于具有更大指令窗口(例如更大输入指令序列)的更简化调度过程。如以上描述的分组去除指令变化并且统一地抽象化这样的变化、由此允许实施简单、同构和统一调度决策做出。以上描述的分组功能增加调度器的吞吐量而未增加调度器的复杂性。例如在用于四个引擎的调度器中，调度器可以派发四组，其中每组具有三个指令。在这样做时，调度器在派发12个指令之时仅处置超定标器复杂性的四个通道。另外，每个块可以包含并行独立组，这进一步增加派发的指令数目。
图21示出根据本发明的一个实施例的多个引擎及其部件的概况图，这些部件包括全局前端提取和调度器和寄存器文件、全局互连以及用于多核处理器的分段式存储器子系统。如在图21中描绘的那样，示出四个存储器片段101-104。存储器片段化分级跨越每个存储器分级(例如L1高速缓存、L2高速缓存和加载存储缓冲器)相同。可以通过存储器全局互连110a在L1高速缓存中的每个L1高速缓存、L2高速缓存中的每个L2高速缓存和加载存储缓冲器中的每个加载存储缓冲器之间交换数据。
存储器全局互连包括路由矩阵，该路由矩阵允许多个核(例如地址计算和执行单元121-124)访问可以在片段式高速缓存分级中的任何点(例如L1高速缓存、加载存储缓冲器和L2高速缓存)存储的数据。图21还描绘地址计算和执行单元121-124可以通过存储器全局互连110a来访问片段101-104中的每个片段的方式。
执行全局互连110b相似地包括路由矩阵，该路由矩阵允许多个核(例如地址计算和执行单元121-124)访问可以在分段式寄存器文件中的任何分段式寄存器文件存储的数据。因此，该核具有通过存储器全局互连110a或者执行全局互连110b对在片段中的任何片段中存储的数据和对在分段中的任何分段中存储的数据的访问。
图21还示出全局前端提取和调度器，该全局前端提取和调度器对于整个机器的视图并且管理寄存器文件分段和片段式存储器子系统的利用。地址生成包括用于片段定义的基础。全局前端提取和调度器通过向每个片段分配指令序列来工作。
图22示出根据本发明的一个实施例的多个片段、多个片段是公共分区调度器互连和以及进入片段的端口。如图在图22中描绘的那样，示出每个分段具有公共分区调度器。该公共分区调度器通过调度在它的相应分段内的指令来工作。这些指令是从全局前端提取和调度器轮流接收的。在这一实施例中，该公共分区调度器被配置为与全局前端提取和调度器配合工作。还示出该分段具有4个读取写入端口，这些读取写入端口提供对操作数/结果缓冲器、线程式寄存器文件和公共分区或者调度器的读取/写入访问。
在一个实施例中，实施非集中式访问过程用于使用互连，并且本地互连运用保留加法器和门限限制器来控制对每个争用的资源——在这一情况下为进入每个分段的端口——的访问。在这样的一个实施例中，核需要保留必需总线并且保留必需端口。
图23示出根据本发明的一个实施例的示例微处理器流水线2300的图。微处理器流水线2300包括提取模块2301，该提取模块实施如以上描述的用于标识和抽取包括执行的指令的过程的功能。在图23的实施例中，提取模块跟随有解码模块2302、分配模块2303、派发模块2304、执行模块2305和引退模块2306。应当指出微处理器流水线2300仅为实施以上描述的本发明的实施例的功能的流水线的一个示例。本领域技术人员将认识可以实施包括以上描述的解码模块的功能的其它微处理器流水线。
出于说明的目的，前文描述参照具体实施例，其未旨在于穷举或者限制本发明。与以上教导一致的许多修改和变化是可能的。选择和描述实施例以便最好地说明本发明的原理及其实际应用以便使本领域其他技术人员能够借助如可以与本发明和各种实施例的特定使用相适的各种修改最好地利用本发明和各种实施例。

Claims (14)

1.一种用于分级地调度指令的微处理器中的方法，其中，所述微处理器包括多个指令队列，所述方法包括：
访问输入指令序列；
将所述输入指令序列分组为多个依赖性分组；
向所述输入指令序列中的每个指令指派依赖性级；
按照依赖性级的顺序将被分组到所述多个依赖性分组中的相同依赖性分组中的指令加载到所述多个指令队列中的相同指令队列中；以及
分派来自所述多个指令队列的指令。
2.如权利要求1所述的方法，其特征在于，所述多个依赖性分组包括可变大小的依赖性分组。
3.如权利要求1所述的方法，其特征在于，所述多个依赖性分组包括固定大小的依赖性分组。
4.如权利要求1所述的方法，其特征在于，移动窗口调度器处理所述多个指令队列中的指令以分派来自指令队列的指令。
5.如权利要求1所述的方法，其特征在于还包括：
生成继承矢量以支持所述多个依赖性分组的执行；以及
将所述多个依赖性分组和所述继承矢量分配给多个引擎。
6.如权利要求1所述的方法，其特征在于，所述多个依赖性分组中的第一依赖性分组和第二依赖性分组被加载到所述多个指令队列中的一指令队列中作为多个半块。
7.如权利要求6所述的方法，其特征在于，所述第一依赖性分组和所述第二依赖性分组被分派给一引擎，其中，依赖性分组中的指令按依赖性级的顺序被堆叠在所述引擎的一组执行单元上，以允许执行给定指令的结果流至用于执行依赖于所述给定指令的指令的执行单元。
8.一种用于分级地调度指令的微处理器，包括：
多个指令队列；以及
调度器组件，所述调度器组件用于：访问输入指令序列，将所述输入指令序列分组为多个依赖性分组，向所述输入指令序列中的每个指令指派依赖性级，按照依赖性级的顺序将被分组到所述多个依赖性分组中的相同依赖性分组中的指令加载到所述多个指令队列中的相同指令队列中，以及分派来自所述多个指令队列的指令。
9.如权利要求8所述的微处理器，其特征在于，所述多个依赖性分组包括可变大小的依赖性分组。
10.如权利要求8所述的微处理器，其特征在于，所述多个依赖性分组包括固定大小的依赖性分组。
11.如权利要求8所述的微处理器，其特征在于，移动窗口调度器处理所述多个指令队列中的指令以分派来自指令队列的指令。
12.如权利要求8所述的微处理器，其特征在于还包括：
多个引擎，其中，所述调度器组件被配置为用于生成继承矢量以支持所述多个依赖性分组的执行并且将所述多个依赖性分组和所述继承矢量分配给所述多个引擎。
13.如权利要求8所述的微处理器，其特征在于，所述多个依赖性分组中的第一依赖性分组和第二依赖性分组被加载到所述多个指令队列中的一指令队列中作为多个半块。
14.如权利要求13所述的微处理器，其特征在于，所述第一依赖性分组和所述第二依赖性分组被分派给一引擎，其中，依赖性分组中的指令按依赖性级的顺序被堆叠在所述引擎的一组执行单元上，以允许执行给定指令的结果流至用于执行依赖于所述给定指令的指令的执行单元。
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