JPS59155162A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS59155162A
JPS59155162A JP58030001A JP3000183A JPS59155162A JP S59155162 A JPS59155162 A JP S59155162A JP 58030001 A JP58030001 A JP 58030001A JP 3000183 A JP3000183 A JP 3000183A JP S59155162 A JPS59155162 A JP S59155162A
Authority
JP
Japan
Prior art keywords
bumps
bump
semiconductor chip
guide
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58030001A
Other languages
English (en)
Inventor
Shuji Watanabe
渡辺　修治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58030001A priority Critical patent/JPS59155162A/ja
Publication of JPS59155162A publication Critical patent/JPS59155162A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H01L2224/14517—Bump connectors having different functions including bump connectors providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （ａ）　　弁明の技術分野 本発明は半導体装置の製造方法に係り、特に１対の半導
体チップを７工−スタクンボンデインク方式によって相
互にバンプ接続する方法の改良に関するものである。
（１））　　技術の背景 一般にハイブリッド構成の半導体装置を製造する場合１
例えば多端子チップ素子同士をワイヤを用いずにバンプ
配設面により構成する７工−スダクン接合方式が知られ
ており、同時に多端子接続が可能であると共に１組立が
容易化される利点を有している。
（Ｃ）　　従来技術と間鵬点 ところで上記したように例えばそれぞれ主表面に複数の
バンクを設けた１対の半導体チックを。
その双方の各対応するパンダ同士を対向させ、さらに亀
ね合せてボンディング法によりバンプ接合を行う方法に
あっては、往々にして相互に当接した６対のバンプの１
方のバンプが圧着の際に、横方向にスリップし、双方の
バンクがずれた状態で接合される・不都合が生じやすい
欠点があり、精度のよいバンプ接合を再現性よく行うこ
とができる方法が要望されている。
（ｄ）　　発明の目的 本発明は上記従来の欠点を排除するため、バンプ接合す
べき１対の半導体チップの各バング配設面に簡単なスリ
ップ防止手段を設けて、再現性よく精良のよいバンプ接
合を行うことができる新規な半導体装置の製造方法を提
供することを目的とするものである。
（Ａ）発明の構成 そし７てこの目的は本発明によれば、それぞれ生麦ｍ１
にバングを設けた１対の牛等体チップを、相、）互のｌ
＜ン１同士を対向させてボンディング接合する方法にお
いて、前記一方の半導体チップのバンプ配設向の周辺部
に複数個のカイトバンプを故けると共に、対応する他方
の半導体チップのバング配設面の同辺部に複数個の保合
バンプを設け、前記一方の半導体チックの各カイトバン
ブに対向して他方の半導体チップの各保合バンブが内接
する形で双方の半導体チップをバング接合するようにし
たことを特徴とする半導体装置の製造方法を提供するこ
とによって達成される。
（ｆ）　　発明の実施例 以下図面を用いて本発明の好ましい実施例について詳細
に説明する。
第１図乃至第３図は本発明に係る半導体装置の製造方法
の一実施例を工程順に示す抑、略斜′視図および＆詰所
面図である。
まず第１図忙示すようにフェースタクンボンデイングす
べき１対・半導体チップ１，２の内の一力の半導体チッ
プｌの各電極接続部に例えば低融点金属のインジウム（
Ｉｎ）％からなる柱状の金属がンフ３をそれぞれ配設す
ると共に、そのバング配設面の尚辺部に、前記金にバン
プ３と同材貿にして有夫の高い複数（本実施例では４仙
１）の駒）形状をηするガイドバンプ４を配設する。ま
た他方の半導体チップ２の各−極接紛部にも例えば低融
点金九のインジクムＣ工ｎ）＃）からなる柱状の金属バ
ンブ５をそれぞれＬＩ！すると共に、そのバンブ１設面
の周辺部に、前記一方の半導体チップ１のバンプ配設１
１１ｊＫｉｔけた各カイトバンブ４に内接するように＠
ｉ数（本実施例では４個）の柱状のインジウム（Ｉｎ）
′４−からなる保合バンブ６を配設しておく。次いで第
２図の廉１面図で示すように、前記一方の半尋＃ヂン７
１上の各カイトバンプ４に対向して他方の半導体チップ
２上の６併、合バンブ６が内接するように６ノ置合せを
行い、双方の各対応する金属バンプ３（！−５同士を亀
ね合せる。しがる彷圧負などのホンティンク法によって
バンブ接合ヲ行うことによシ、第３図に示すように他方
の半導体チップ２土の各保合パン７゛６が対向する一方
の半導体チップ］の各カイトバンブ４に内ｉｔ＜合され
て、接合される各企恥・、／くンフ３と５胎Ｊの横ずれ
が防止され、１！ｌ￥良のよい扼実なバンプ接合を容易
に行うことが句能となる。なお上記バング接合に際して
前記カイトノくンフー４および保合バンプ６の先端面は
、天々対向する半導体チップ１，２ｉｉｊに当接させた
場合の例で図示しているが、当接しない構成であっても
充分に目的は達成される。さらに上記のようにカイト／
９ン７４および保合がンプ６の先端面が大々対向する半
導体チップ１．２’ｒｆｒｌＪに当接さぞる構成にすれ
ば、前記カイトバンブ゛４および保合パンクロをがンプ
接合時のスペーツ゛として湘ねさせることもできる。そ
の４ｒ＋・４ｊＩ記カイＦノ（ン７の形状として超１本
実施例の如き鉤形状のものに限定されるもので／′ｉな
く５例えはコの字形状あるいはＵ字形状％１−にシても
よい。
ｆｇ）　　＊明の効架− 以上の８兄明から明らかなようにΔ・弁明に係る半導体
装置の製り方法によれば、それぞれ主表面にバングを設
けた１対の半２０１体チックを、相互のノくン７同士を
対向させてフェースククンポンテインクを行う際に、接
合される灼回バンフ向での位置ずれが解消され　精良の
よい角実なバンプ接合を再夕木よく行うことがＥＪ能と
なる。よってこの沖のフインク接合を必にとするハイフ
リント程・ｖ成の半導体装置１例えば光検知素７アレイ
（！−献アレイの佑勺処坤紫子とを金紐、バンフ接合に
よって一体に構成する半鄭休撮伽装置の製造等に画用し
て締めてη利である、 製造方法の一実施例を１稈順に船、明する樵、ｆｌ（、
斜視。
図および壮・：ｌｌｌ？！断面図である。
図面におい〜て、１．２は生得りチンフ、３．５ハ金糾
バンブ、４はカイドバンフ、６は保合パン７を示す。

Claims (1)

    【特許請求の範囲】
  1. それぞれ主表面にバンプを設けた１対の半導体チップを
    相互のバンプ同士を対向させてホンデインク接合する方
    法において、Ｐ！０記一方の半導体チックの／＜ンプ配
    設面の同辺部に複数個のカイトバンプを設けると共に、
    対応する他方の半導体チップのバンプ配設面の周辺部に
    複数個の保合バンプを設け、前記一方の半導体チックの
    各カイトバンプに対向して他方の半導体チップの各係合
    バンプが内接する形で双方の半導体チックをパンダ接合
    するようにしたことを特徴とする半導体装置の製造方法
    。
JP58030001A 1983-02-23 1983-02-23 半導体装置の製造方法 Pending JPS59155162A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58030001A JPS59155162A (ja) 1983-02-23 1983-02-23 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58030001A JPS59155162A (ja) 1983-02-23 1983-02-23 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS59155162A true JPS59155162A (ja) 1984-09-04

Family

ID=12291666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58030001A Pending JPS59155162A (ja) 1983-02-23 1983-02-23 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59155162A (ja)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6189657A (ja) * 1984-10-08 1986-05-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
EP0532297A1 (en) * 1991-09-10 1993-03-17 Fujitsu Limited Process for flip-chip connection of a semiconductor chip
FR2742000A1 (fr) * 1995-11-30 1997-06-06 Sgs Thomson Microelectronics Composant semiconducteur a montage par brasure
US5656507A (en) * 1992-01-28 1997-08-12 British Telecommunications Public Limited Company Process for self-aligning circuit components brought into abutment by surface tension of a molten material and bonding under tension
US5700715A (en) * 1994-06-14 1997-12-23 Lsi Logic Corporation Process for mounting a semiconductor device to a circuit substrate
EP1589570A1 (en) * 2003-01-16 2005-10-26 Sony Corporation Semiconductor device and process for producing the same
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
WO2018134547A1 (fr) * 2017-01-23 2018-07-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'un dispositif electronique et dispositif electronique

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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