JPS59139429A - バツフア制御装置 - Google Patents

バツフア制御装置

Info

Publication number
JPS59139429A
JPS59139429A JP1331083A JP1331083A JPS59139429A JP S59139429 A JPS59139429 A JP S59139429A JP 1331083 A JP1331083 A JP 1331083A JP 1331083 A JP1331083 A JP 1331083A JP S59139429 A JPS59139429 A JP S59139429A
Authority
JP
Japan
Prior art keywords
data
input
output control
control
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1331083A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63831B2 (enExample
Inventor
Kenichi Maeda
健一 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1331083A priority Critical patent/JPS59139429A/ja
Publication of JPS59139429A publication Critical patent/JPS59139429A/ja
Publication of JPS63831B2 publication Critical patent/JPS63831B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
JP1331083A 1983-01-28 1983-01-28 バツフア制御装置 Granted JPS59139429A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1331083A JPS59139429A (ja) 1983-01-28 1983-01-28 バツフア制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1331083A JPS59139429A (ja) 1983-01-28 1983-01-28 バツフア制御装置

Publications (2)

Publication Number Publication Date
JPS59139429A true JPS59139429A (ja) 1984-08-10
JPS63831B2 JPS63831B2 (enExample) 1988-01-08

Family

ID=11829597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1331083A Granted JPS59139429A (ja) 1983-01-28 1983-01-28 バツフア制御装置

Country Status (1)

Country Link
JP (1) JPS59139429A (enExample)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040047A (enExample) * 1973-08-14 1975-04-12
JPS539433A (en) * 1976-07-13 1978-01-27 Fujitsu Ltd Buffer memory control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040047A (enExample) * 1973-08-14 1975-04-12
JPS539433A (en) * 1976-07-13 1978-01-27 Fujitsu Ltd Buffer memory control system

Also Published As

Publication number Publication date
JPS63831B2 (enExample) 1988-01-08

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