JPS59135736A - 半導体装置製造方法 - Google Patents

半導体装置製造方法

Info

Publication number
JPS59135736A
JPS59135736A JP58010396A JP1039683A JPS59135736A JP S59135736 A JPS59135736 A JP S59135736A JP 58010396 A JP58010396 A JP 58010396A JP 1039683 A JP1039683 A JP 1039683A JP S59135736 A JPS59135736 A JP S59135736A
Authority
JP
Japan
Prior art keywords
semiconductor element
lead frame
collet
semiconductor device
preformed material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58010396A
Other languages
English (en)
Inventor
Yoshio Kubo
久保 良夫
Yoshiyuki Matsui
良行 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP58010396A priority Critical patent/JPS59135736A/ja
Publication of JPS59135736A publication Critical patent/JPS59135736A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301Bonding head
    • H01L2224/75302Shape
    • H01L2224/75303Shape of the pressing surface
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
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    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
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    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ;λ、技術分野 本発明は半導体装置製造方法に関する。
b、従来技術及びその欠点 第1図は従来の半導体製造方法により製造[7たトラン
ジスタの構造を示す断面図である。
図において、1はリードフレーム1.2はリードフレー
ム1に半田等のプリフォーム材3を介(、て融着された
半導体素子であって、この半導体素子2の表面にはポン
ディングパツド2aが、裏面には適宜の裏メタル2bが
そねぞれ形成されている。そして、ポンディングパッド
2aとリードフレーム1の所定端子との間は金線又はA
6線4により接続されている。
而して、半導体素子2をリードフレーム1に上記のよう
に融着さゼる場合、従来は以−ドのようにしていた。即
ち、まず、加熱したリードフレーム1にプリフォーム材
3を敷設する。ぞして、コレットに吸着させた半導体素
子を前記プリフォーム材3に一定荷重で押圧しつつスク
ラブ又は低周波振動によるバイブレーションを行うこと
により融稲させていた。
しかしながら、上記方法によると、プリフ(−ム材3内
に気泡3aが生じ易く、その結果、プリフォーム材3の
熱伝導が悪くなり、熱抵抗が増大するので半導体装置の
信頼性上好ましくない。C1にパワートランジスタ、パ
ワーIC等の半導体装置にあっては、接合部に発生した
熱を急速に逃かず必要があるか、気泡3aによりプリフ
ォーム材3の熱伝導が悪化すると接合部に於ijる温度
−1−昇か急激となりついには熱破壊に到ることかある
吉いう欠点があった。
C0目的 本発明は、プリフォーム祠1ζ気泡が牛じることのない
014導体製造方法を提供することを1」的とする3゜ d、実施例 ff12図は本発明に係る半導体製造方法の一実施例を
示す説明図である。
図において第1図と同一物には同7コ1号を付しである
。而して、5は腕部材であ−)で、その先端近傍にはコ
レット6か開「1部を下にした状態で取付けられている
。このコレツl−6は半導体素子2を図示するように吸
着する。そしで、ヒータフロック7により加熱されたリ
ードフレーム1に置かれたプリフォーム祠3に前記半導
体素子2を一定萄重で押圧するとともに、前記半イ、(
体素子2に腕部材5及びコレット6を介して超音波振動
を与えることにより、半導体素子2をリードフレーム1
に融着さぜる4゜ e、効果 本発明によりは、プリフォーム祠の内部に分散し7てい
た気泡か超音波振動により外部へ逃ける結4、ノリフオ
ーム相の内部には気泡かはとんど存在しなくなるのて、
グリフ1−ム祠の熱(ム導も良好となり、半郷体装的′
が熱破壊するおそねがなくなる。
【図面の簡単な説明】
第1図は従来の半導体装置製遣方V、により製ス告した
トランジスタの構造を示す断面図、第2図は本発明に係
る半導体装置製造方法の一実施例を小ず説明図である。 1・・・リー ドフレーム、2・・・半導体素子、3・
・・プリフォーム祠、5・・・腕部材、6・・・コレッ
ト、7・・・に−タブに1ツク。 特許出願人 ローム株式会社 代理人弁理士大西イ冶

Claims (1)

    【特許請求の範囲】
  1. (月 超音波振動を与えつつ半導体素子とリードフレー
    ムとをプリフォーム材を介して融着させることを特徴と
    する半導体装置製造方法。
JP58010396A 1983-01-24 1983-01-24 半導体装置製造方法 Pending JPS59135736A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58010396A JPS59135736A (ja) 1983-01-24 1983-01-24 半導体装置製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58010396A JPS59135736A (ja) 1983-01-24 1983-01-24 半導体装置製造方法

Publications (1)

Publication Number Publication Date
JPS59135736A true JPS59135736A (ja) 1984-08-04

Family

ID=11748962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58010396A Pending JPS59135736A (ja) 1983-01-24 1983-01-24 半導体装置製造方法

Country Status (1)

Country Link
JP (1) JPS59135736A (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527619A (en) * 1978-08-17 1980-02-27 Mitsubishi Electric Corp Die bonding device
JPS5529544B1 (ja) * 1970-08-28 1980-08-04

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5529544B1 (ja) * 1970-08-28 1980-08-04
JPS5527619A (en) * 1978-08-17 1980-02-27 Mitsubishi Electric Corp Die bonding device

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