JPS59125638A - 半導体素子分離の製造方法 - Google Patents

半導体素子分離の製造方法

Info

Publication number
JPS59125638A
JPS59125638A JP31483A JP31483A JPS59125638A JP S59125638 A JPS59125638 A JP S59125638A JP 31483 A JP31483 A JP 31483A JP 31483 A JP31483 A JP 31483A JP S59125638 A JPS59125638 A JP S59125638A
Authority
JP
Japan
Prior art keywords
film
silicon
oxide film
groove
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31483A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6351537B2 (enrdf_load_stackoverflow
Inventor
Keimei Mikoshiba
御子柴 啓明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP31483A priority Critical patent/JPS59125638A/ja
Publication of JPS59125638A publication Critical patent/JPS59125638A/ja
Publication of JPS6351537B2 publication Critical patent/JPS6351537B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP31483A 1983-01-05 1983-01-05 半導体素子分離の製造方法 Granted JPS59125638A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31483A JPS59125638A (ja) 1983-01-05 1983-01-05 半導体素子分離の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31483A JPS59125638A (ja) 1983-01-05 1983-01-05 半導体素子分離の製造方法

Publications (2)

Publication Number Publication Date
JPS59125638A true JPS59125638A (ja) 1984-07-20
JPS6351537B2 JPS6351537B2 (enrdf_load_stackoverflow) 1988-10-14

Family

ID=11470446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31483A Granted JPS59125638A (ja) 1983-01-05 1983-01-05 半導体素子分離の製造方法

Country Status (1)

Country Link
JP (1) JPS59125638A (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6340337A (ja) * 1986-07-07 1988-02-20 テキサス インスツルメンツ インコ−ポレイテツド 集積回路分離法
US4892614A (en) * 1986-07-07 1990-01-09 Texas Instruments Incorporated Integrated circuit isolation process
JPH09153542A (ja) * 1995-11-30 1997-06-10 Nec Corp 半導体装置の製造方法
KR100329606B1 (ko) * 1995-06-02 2002-10-25 주식회사 하이닉스반도체 반도체소자의소자분리절연막형성방법
KR100361762B1 (ko) * 1995-11-06 2003-02-11 주식회사 하이닉스반도체 반도체소자의소자분리방법

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02179246A (ja) * 1988-12-28 1990-07-12 Fanuc Ltd ビルトインモータのステータ構造
JPH0617345U (ja) * 1992-07-22 1994-03-04 東洋電機製造株式会社 フレーム無しの交流機の固定子

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6340337A (ja) * 1986-07-07 1988-02-20 テキサス インスツルメンツ インコ−ポレイテツド 集積回路分離法
US4892614A (en) * 1986-07-07 1990-01-09 Texas Instruments Incorporated Integrated circuit isolation process
KR100329606B1 (ko) * 1995-06-02 2002-10-25 주식회사 하이닉스반도체 반도체소자의소자분리절연막형성방법
KR100361762B1 (ko) * 1995-11-06 2003-02-11 주식회사 하이닉스반도체 반도체소자의소자분리방법
JPH09153542A (ja) * 1995-11-30 1997-06-10 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS6351537B2 (enrdf_load_stackoverflow) 1988-10-14

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